Apparatus and method for automatically generating circuit designs that meet user output requirements

• US 6,539,534 B1
• Filed: 03/14/2001
• Issued: 03/25/2003
• Est. Priority Date: 08/25/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Bennett, David W.
• Primary Examiner(s): Wong, Don
• Assistant Examiner(s): Dinh, Trinh Vo
• Application Number:
  US09/809,597
• Time in Patent Office: 741 Days
• Field of Search: G06/F 1.750, H03/K 1.900, 716/16, 716/17, 716/18, 716/4, 716/12, 716/13, 716/1, 716/2, 716/3, 716/5, 716/14, 716/15, 326/39
• US Class Current: 716/102
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method for generating a circuit design using specified input characteristics and desired output characteristics. An algorithm is used to generate candidate circuits from the desired circuit characteristics. The candidate circuit is tested with a stimulating test apparatus to provide actual output characteristics in response to the specified input characteristics. If the actual and desired output characteristics do not match, the candidate circuit is modified and re-tested. The design process may be automated or manual.

Claims

1. A method of designing a circuit to be implemented in a PLD comprising the steps of:

defining a designed circuit behavior having desired output characteristics resulting from specified input characteristics;

generating a candidate circuit for performing the desired circuit behavior using an algorithm other than a genetic algorithm;

programming the PLD to implement the candidate circuit;

stimulating the PLD with the specified input characteristics and obtaining actual output characteristics of the PLD resulting from the PLD stimulation; and

comparing the actual output characteristics of the PLD to the desired output characteristics of the desired circuit behavior.

2. The method of claim 1 wherein the desired circuit behavior is described as output waveforms resulting from a set of input waveforms.

3. The method of claim 1 wherein the desired circuit behavior is described using a test bench.

4. The method of claim 1 wherein the candidate circuit is generated using a logic synthesis algorithm.

5. The method of claim 4 wherein when the step of comparing the outputs of the candidate circuit to the desired outputs fails to result in a match, a different candidate circuit is generated and subsequent steps are repeated.

6. The method of claim 5 wherein the different candidate circuit is generated by resynthesizing the candidate circuit.

7. The method of claim 6 wherein the step of resynthesizing the candidate circuit is performed using the logic synthesis algorithm.

8. The method of claim 1 further comprising the steps of:

evolving the candidate circuit into a different candidate circuit based on the comparison of the actual output characteristics of the PLD to the desired output characteristics of the desired circuit behavior; and

recursively evaluating the different candidate circuit in the same manner as the candidate circuit.

9. The method of claim 8 wherein the different candidate circuit is generated by a simulated annealing algorithm.

10. The method of claim 1 wherein the step of stimulating the PLD and obtaining actual output characteristics is performed by a printed circuit board attached to a computer.

11. The method of claim 1 wherein when the step of comparing the outputs of the candidate circuit to the desired outputs fails to result in a match, a different candidate circuit is generated and subsequent steps are repeated.

12. The method of claim 11 wherein the different candidate circuit is generated by resynthesizing the circuit.

13. The method of claim 11 wherein the different candidate circuit is generated using a genetic algorithm.

14. The method of claim 11 wherein the different candidate circuit is generated by a simulated annealing algorithm.

15. The method of claim 1, wherein the desired circuit behavior defined depends on the PLD implementing the circuit.

16. An apparatus for designing a circuit to be implemented in a PLD comprising:

means for defining a desired circuit behavior in terms of the desired output characteristics resulting from specified input characteristics;

means other than a genetic algorithm for generating a candidate circuit for performing the desired circuit behavior;

a PLD for implementing the candidate circuit;

stimulation hardware for stimulating the PLD with the specified input characteristics and obtaining actual output characteristics of the PLD resulting from the PLD stimulation; and

means for comparing the actual output characteristics of the PLD to the desired output characteristics of the desired circuit behavior.

17. The apparatus of claim 16 further comprising means for recursively adapting the candidate circuit.

18. The apparatus of claim 16 further comprising means for automating the design of the circuit.

19. A method of designing a circuit comprising the steps of:

defining a desired circuit behavior having desired output characteristics resulting from specified input characteristics;

generating a first candidate circuit for performing the desired circuit behavior using an algorithm other than a genetic algorithm;

testing the first candidate circuit to obtain actual output characteristics;

comparing the actual output characteristics to the desired output characteristics;

evolving the first candidate circuit into a second candidate circuit when the actual output characteristics do not match the desired output characteristics; and

recursively evaluating the second candidate circuit in the same manner as the first candidate circuit.

20. A method of designing a circuit comprising the steps of:

defining a desired circuit behavior having desired output characteristics resulting from specified input characteristics;

generating a first candidate circuit for performing the desired circuit behavior;

testing the first candidate circuit to obtain actual output characteristics;

comparing the actual output characteristics to the desired output characteristics;

evolving the first candidate circuit into a second candidate circuit using simulated annealing when the actual output characteristics do not match the desired output characteristics; and

recursively evaluating the second candidate circuit in the same manner as the first candidate circuit.