Formation of antifuse structure in a three dimensional memory

• US 6,541,312 B2
• Filed: 12/22/2000
• Issued: 04/01/2003
• Est. Priority Date: 12/22/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M., Knall, N. Johan, Vyvoda, Michael A.
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US09/746,083
• Publication Number:
  US 20030003632A1
• Time in Patent Office: 830 Days
• Field of Search: 438/131, 438/467, 438/600, 257/550, 365/175, 365/159
• US Class Current: 438/131
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material.

In the second embodiment of the present invention the array comprises a first plurality of spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric is recessed below the top surface of the semiconductor material. An antifuse material is formed on the top semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor film is formed on the antifuse material.

Claims

1. A method of forming a memory comprising:

forming a first plurality of spaced apart rail-stacks having a top semiconductor film;

forming a dielectric film having a top surface between said plurality of first rail-stacks;

etching said semiconductor film of said first plurality of spaced apart rail-stacks so that said semiconductor film is recessed below said top surface of said dielectric film;

forming an antifuse material on said etched semiconductor film of said first plurality of spaced apart rail-stacks; and

forming a second plurality of spaced apart rail-stacks on said antifuse material, said second plurality of spaced apart rail-stacks having a lower semiconductor film on said antifuse material.

2. The method of claim 1 wherein said antifuse material is an oxide film grown on said etched semiconductor surface of said first plurality of spaced apart rail-stacks.

3. The method of claim 2 wherein said oxide is constrained by the sidewalls of said dielectric film.

4. The method of claim 1 wherein said antifuse material is an oxide film deposited onto said semiconductor material on said first plurality of spaced apart rail-stacks and on said dielectric film between said rail-stacks.

5. The method of claim 4 wherein said recess is less than the thickness of said antifuse material.

6. The method of claim 4 wherein said antifuse material is deposited to a thickness sufficient to completely fill said recess.

7. The method of claim 1 wherein said semiconductor material is etched with a nonpolymer forming method.

8. The method of claim 1 wherein said etching utilizes a NF₃ plasma.

9. The method of claim 1 wherein said recess forming etch is a wet etch comprising nitric acid and hydrofluoric acid.

10. The method of claim 1 further comprising after recessing said semiconductor material of said first plurality of spaced apart rail-stacks, sputter etching said dielectric fill so as to form sloped sidewalls.

11. The method of claim 1 wherein said semiconductor material of said first plurality of spaced apart rail-stacks is recessed between 5-150 Å

below the top surface of said dielectric fill material.

12. A method of forming a memory comprising:

forming a first plurality of spaced apart rail-stacks having a top semiconductor film;

forming a dielectric film between said first plurality of spaced apart rail-stacks;

etching said dielectric film below the top surface of said semiconductor material of said first plurality of spaced apart rail-stacks to form a convex corner at the top edge of said semiconductor material;

forming an antifuse material on and over said corner of said semiconductor material of said first plurality of spaced apart rail-stacks; and

forming a second plurality of spaced apart rail-stacks on said antifuse material, said second plurality of spaced apart rail-stacks having a lower semiconductor film on said antifuse material.

13. The method of claim 12 further comprising sputter etching said semiconductor material after recessing said oxide below the top surface of said semiconductor material and before depositing said antifuse material.

14. The method of claim 13 wherein said sputter etch bevels said corner of said semiconductor material.

15. The method of claim 12 wherein said antifuse material is an oxide deposited by plasma enhanced chemical vapor deposition process.

16. The method of claim 15 wherein said plasma enhanced chemical vapor deposition process is a high density plasma process.

17. The method claim 12 wherein said oxide is recessed between 5-150 Å

below the top surface of said semiconductor material of said first plurality of spaced apart rail-stacks.

18. The method of claim 12 wherein said dielectric is a grown oxide.

19. The method of claim 18 wherein said oxide is grown with a high density plasma process (HDP).

20. The method of claim 19 wherein said oxide is grown with a thermal process.

21. A method for fabricating a three-dimensional array comprising:

forming a silicon layer having an upper surface;

forming a masking layer over the silicon layer;

patterning the masking layer;

etching at least the silicon layer in alignment with the patterned masking layer to define memory array features, the features having an upper surface;

filling between the features with a dielectric material which is softer than the masking layer to a level below the upper surface of the features;

planarizing the dielectric material with the masking layer acting as a stop;

removing the patterned masking layer; and

forming an antifuse layer on the upper surface of the features such that the features protrude into the antifuse layer.

22. The method defined by claim 21 wherein the antifuse layer is formed by a blanket deposition covering the features and the dielectric material.

23. The method defined by claim 22 wherein the antifuse layer is silicon dioxide.

24. The method defined by claim 22 wherein the silicon layer is formed by an annealing an amorphous silicon layer.

25. The method defined by claim 24 wherein the silicon dioxide is deposited by chemical-vapor-deposition (CVD).

26. The method defined by claim 21 wherein the antifuse layer is grown from the silicon layer.

27. The method defined by claim 26 wherein the grown silicon dioxide layer is grown in a steam atmosphere.

28. The method defined by claims 21 wherein the masking layer comprises a top silicon nitride layer and a lower silicon dioxide layer.

29. The method defined by claim 28 wherein dielectric material is silicon dioxide.

30. The method defined by claim 29 wherein the planarization comprises chemical-mechanical polishing.

31. The method defined by claim 30 wherein the silicon layer is a polysilicon layer.

32. The method defined by claim 30 wherein the polysilicon layer is a doped layer.

33. A method for fabricating a three-dimensional array comprising:

forming a silicon layer having an upper surface;

forming a masking layer over the silicon layer, the masking layer having a lower surface in contact with the upper surface of the silicon layer;

patterning the masking layer;

etching at least the silicon layer in alignment with the patterned masking layer to define memory array features, each of the features having an upper surface;

filling between the features with a dielectric material which is softer than the masking layer to a level above the upper surface of the features;

planarizing the dielectric material with the masking layer acting as a stop;

removing the patterned masking layer;

forming an antifuse layer on the upper surface of the features such that the antifuse layer has recessions.

34. The method defined by claim 33 wherein the silicon layer is formed from an amorphous silicon layer.

35. The method defined by claim 33 wherein the antifuse layer is a blanket deposition covering the features and the dielectric material.

36. The method defined by claim 35 wherein the antifuse layer is silicon dioxide.

37. The method defined by claim 36 here silicon dioxide is deposited by chemical-vapor-deposition (CVD).

38. The method defined by claim 37 wherein the masking layer comprises a material selected from the group consisting of silicon nitride, titanium nitride, tungsten and tungsten silicide.

39. The method defined by claim 38 wherein the dielectric material comprises silicon dioxide.

40. The method defined by claim 39 wherein the planarization step comprises the use of chemical-mechanical polishing.

41. The method defined by claim 40 wherein the silicon layer is a polysilicon layer.

42. The method defined by claim 41 wherein the polysilicon layer is doped.

43. A method for forming a three-dimensional memory array comprising:

forming a masking layer on an upper surface of a silicon layer;

forming memory features from the silicon layer using the masking layer;

filling spaces between the memory features with a filling material which etches more quickly than the masking layer, to a level below the upper surface of the silicon layer;

planarizing the filling material using the masking layer as an etchant stop;

removing the masking layer;

forming an antifuse layer on the memory features, such that the antifuse layer is thinner at the edges of the features than midway between the edges of the features.

44. The method defined by claim 43 wherein the planarization comprises chemical-mechanical polishing.

45. The method defined by claim 44 wherein the silicon comprises doped polysilicon.

46. The method defined by claim 45 wherein the filling comprises silicon dioxide.

47. The method defined by claims 43 wherein the antifuse layer comprises a deposited silicon dioxide layer.

48. The method defined by claims 43 wherein the antifuse layer comprises a grown silicon dioxide layer.

49. The method defined by claim 47 wherein the masking layer comprises a top silicon nitride layer and a lower silicon dioxide layer.

50. The method defined by claim 48 wherein the masking layer comprises silicon nitride.

51. The method defined by claim 45 wherein the memory features comprise parallel, spaced-apart lines.

52. A method for fabricating a three-dimensional memory array comprising:

forming a polysilicon layer;

forming a masking layer having an upper silicon nitride layer and a lower silicon dioxide layer over the polysilicon layer on an upper surface of the polysilicon layer;

patterning the masking layer;

etching at least the polysilicon layer in alignment with the patterned masking layer to define parallel, spaced-apart memory lines;

filling spaces between the memory lines with a dielectric material which polishes more readily than silicon nitride to a level below the upper surface of the polysilicon memory lines;

polishing the dielectric material with the silicon nitride layer acting as a polish stop;

removing the silicon nitride layer;

forming a silicon dioxide layer over the polysilicon lines such that the silicon dioxide layer is thinner at the edges of the lines than at the center of the lines.

53. The method defined by claim 52 wherein the forming of the polysilicon comprises annealing an amorphous silicon layer.

54. The method defined by claim 52 wherein the silicon dioxide layer is a grown layer grown from the polysilicon lines.

55. The method defined by claim 54 wherein the silicon dioxide layer is grown in a steam atmosphere.

56. The method defined by claim 52 wherein the silicon dioxide layer is a deposited layer.

57. The method defined by claims 52 or 56 wherein the polysilicon lines are doped with a first conductivity-type dopant.

58. The method defined by claim 57 wherein another layer of polysilicon doped with a second conductivity type dopant is deposited over the silicon dioxide layer.