Thin film semiconductor device and production method for the same

• US 6,541,795 B2
• Filed: 12/05/2001
• Issued: 04/01/2003
• Est. Priority Date: 06/14/1994
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohtani, Hisashi, Kusumoto, Naoto, Takemura, Yasuhiko
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US10/001,819
• Publication Number:
  US 20020055209A1
• Time in Patent Office: 482 Days
• Field of Search: 257/66, 257/72, 438/151, 438/166
• US Class Current: 257/66
• CPC Class Codes: C30B 1/023 from solids with amorphous structure
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02672 using crystallisation enhancing elements
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object of the present invention is to provide a TFT with which better characteristics can be obtained using a good crystalline silicon film. An amorphous semiconductor film having a thickness of 400 Å or more is formed on an insulating surface, is crystallized by heat annealing or photo annealing or the combined use thereof, and is wholly or selectively etched to form a region having a thickness of 300 Å or less. This is used as a channel-forming region in a TFT.

Claims

1. A semiconductor device comprising:

a substrate;

a semiconductor layer comprising a first portion and a second portion wherein the first portion is thinner than the second portion;

a source region and a drain region provided in the semiconductor layer, at least one of the source region and drain region provided in the first and second portions;

a channel region between the source and drain regions, provided in the first portion; and

a gate electrode provided adjacent to the channel region with an insulating film interposed therebetween,

wherein a peripheral portion of the semiconductor layer is thinned and an edge portion of a least one of the source and drain region is in the peripheral portion, and

wherein the first portion if 300 Å

or less.

2. A device according to claim 1 wherein the semiconductor layer is a crystalline layer.

3. A device according to claim 1 wherein the semiconductor layer comprises silicon.

4. A device according to claim 1 wherein a thickness of the second portion of the source and drain regions is the same as a thickness of the channel region.

5. A device according to claim 1 wherein the insulating film has a thickness of 500Å

or less.

6. A semiconductor device comprising:

a substrate;

a semiconductor layer comprising a first portion and a second portion wherein the first portion is thinner than the second portion;

a source region and a drain region provided in the semiconductor layer, at least one of the source region and drain region provided in the first and second portions;

a channel region between the source and drain regions, provided in the first portion; and

a gate electrode provided adjacent to the channel region with an insulating film interposed therebetween,

wherein a peripheral portion of the semiconductor layer is thinned and an edge portion of a least one of the source and drain region is in the peripheral portion.

7. A device according to claim 6 wherein a thickness of the second portion of the source and drain regions is the same as a thickness of the channel region.

8. A device according to claim 6 wherein the semiconductor layer is a crystalline layer.

9. A device according to claim 6 wherein the semiconductor layer comprises silicon.

10. A device according to claim 6 wherein the insulating film has a thickness of 500 or less.

11. A semiconductor device comprising:

a substrate;

a semiconductor layer formed over the substrate, the semiconductor layer including at least source and drain regions and a channel region therebetween, wherein each of the source and drain regions has a first portion having a larger thickness than the channel region,

wherein each of the source and drain regions has a second portion at a periphery of the source and drain regions, said second portion having a smaller thickness than the first portion.

12. A device according to claim 11 wherein a thickness of the second portion of the source and drain regions is the same as a thickness of the channel region.

13. A device according to claim 11 wherein the semiconductor layer is a crystalline layer.

14. A device according to claim 11 wherein the semiconductor layer comprises silicon.

15. A semiconductor device comprising:

a substrate;

a plurality of pixels in a matrix form over the substrate, each of the plurality of the pixels comprising a first thin film transistor; and

a driving circuit comprising a second thin film transistor over the substrate,

wherein the forst thin film transistor comprises a semiconductor layer and a peripheral portion of the semiconductor layer is thinned, and

wherein an edge portion of a least one of the source and drain regions in the semiconductor layer is in the peripheral portion.

16. A device according to claim 15 wherein the device further comprises a pixel electrode connected with the first thin film transistor.

17. A device according to claim 15 wherein the first the film transistor comprises a source region, a drain region, and a channel region between the source and drain regions, and a thickness of the channel region is thinner than that of the source and drain regions.

18. A device according to claim 15 wherein a peripheral portion of the active layer is thinned.

19. A semiconductor device comprising:

a substrate;

a plurality of pixels in a matrix form over the substrate, each of the plurality of the pixels comprising a first thin film transistor; and

a driving circuit comprising a second thin film transistor over the substrate,

wherein the first thin film transistor comprises a semiconductor layer and a peripheral portion of the semiconductor layer is thinned,

wherein an edge portion of a least one of the source and drain regions in the semiconductor layer is in the peripheral portion, and

wherein the active layer of the first thin film transistor is 300 Å

or less.

20. A device according to claim 19 wherein the first the film transistor comprises a source region, a drain region, and a channel region between the source and drain regions, and a thickness of the channel region is thinner than that of the source and drain regions.

21. A device according to claim 19 wherein the device further comprises a pixel electrode connected with the first thin film transistor.

22. A device according to claim 19 wherein a peripheral portion of the active layer is thinned.