Low voltage planar power MOSFET with serpentine gate pattern

• US 6,541,820 B1
• Filed: 03/28/2000
• Issued: 04/01/2003
• Est. Priority Date: 03/28/2000
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Bol, Igor
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Diaz, Jose R.
• Application Number:
  US09/536,903
• Time in Patent Office: 1,099 Days
• Field of Search: 257/408, 257/341, 257/343, 257/344, 257/357, 257/358, 257/359, 257/360, 257/363, 257/342, 257/409, 257/355, 257/365, 257/401, 438/305
• US Class Current: 257/341
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very large channel width per unit area.

Claims

1. A power MOSFET comprising:

a die of monocrystaline silicon having an upper junction receiving surface;

an elongated strip of gate oxide fixed to said upper surface and overlying a shallow invertible channel region of one conductivity type and a conductive polysilicon gate overlying said strip of gate oxide;

a first and a second region of the other of said conductivity types disposed on opposite sides of said elongated strip and defining source/drain regions, said first and said second regions extending to a depth below that of said invertible channel;

said first and second regions each having lightly doped segments disposed beneath said elongated strip and a central more highly doped contact region, whereby said first and second regions are laterally connected together when said invertible channel region is inverted; and

a plurality of spaced contacts electrically connected to said conductive polysilicon gate, and to said first and second regions,

wherein said elongated strip follows a serpentine path over said upper surface.

2. The power MOSFET of claim 1, wherein said invertable channel has a depth of about 0.2 to about 0.3 microns.

3. The power MOSFET of claim 2, wherein said elongated strip has a width of about 1.5 microns.

4. The power MOSFET of claim 2, wherein each of said polysilicon gate and first and second regions receive a respective plurality of spaced contacts along their length.

5. The power MOSFET of claim 4, wherein said spaced contacts for said polysilicon gate and said first and second regions are aligned along respective straight lines.

6. The power MOSFET of claim 1, wherein each of said polysilicon gate and first and second regions receive a respective plurality of spaced contacts along their length.

7. The power MOSFET of claim 6, wherein said spaced contacts for said polysilicon gate and said first and second regions are aligned along respective straight lines.