Silicon pressure micro-sensing device and the fabrication process
First Claim
1. A silicon pressure micro-sensing device comprising:
- an N-type epitaxial layer comprising;
a plurality of piezo-resistance sensing units, for sensing pressure, in said N-type epitaxial layer;
a passivation, for preventing inappropriate etching from etchant in the process, on an upper surface of said N-type epitaxial layer;
a plurality of device pads formed on an upper surface of the passivation and connected to leads of an external circuit;
a plurality of holes which go through said N-type epitaxial layer and passivation and act as passages for the etchant; and
an insulating membrane on the upper surface of said passivation to seal said plurality of holes; and
a P-type (100) substrate with a taper chamber and on a lower surface of said N-type epitaxial layer.
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Abstract
The invention is a silicon pressure micro-sensing device and the fabrication process thereof. The silicon pressure micro-sensing device includes a pressure chamber, and is constituted of a P-type substrate with a taper chamber and an N-type epitaxial layer thereon. On the N-type epitaxial layer are a plurality of piezo-resistance sensing units which sense deformation caused by pressure. The fabrication pressure of the silicon pressure micro-sensing device includes a step of first making a plurality of holes on the N-type epitaxial layer to reach the P-type substrate beneath. Then, by an anisotropic etching stop technique, in which etchant pass through the holes, a taper chamber is formed in the P-type substrate. Finally, an insulating material is applied to seal the holes, thus attaining the silicon pressure micro-sensing device that is able to sense pressure differences between two ends thereof.
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2 Claims
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1. A silicon pressure micro-sensing device comprising:
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an N-type epitaxial layer comprising;
a plurality of piezo-resistance sensing units, for sensing pressure, in said N-type epitaxial layer;
a passivation, for preventing inappropriate etching from etchant in the process, on an upper surface of said N-type epitaxial layer;
a plurality of device pads formed on an upper surface of the passivation and connected to leads of an external circuit;
a plurality of holes which go through said N-type epitaxial layer and passivation and act as passages for the etchant; and
an insulating membrane on the upper surface of said passivation to seal said plurality of holes; and
a P-type (100) substrate with a taper chamber and on a lower surface of said N-type epitaxial layer. - View Dependent Claims (2)
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Specification