Semiconductor device manufacturing method including forming step of SOI structure and semiconductor device having SOI structure

• US 6,541,861 B2
• Filed: 06/29/2001
• Issued: 04/01/2003
• Est. Priority Date: 06/30/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takase, Tamao, Higashi, Kazuyuki, Shibata, Hideki
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): GREENE, PERSHELLE L
• Application Number:
  US09/893,454
• Publication Number:
  US 20020011670A1
• Time in Patent Office: 641 Days
• Field of Search: 257/347, 257/349, 257/354, 257/507, 257/510, 257/751, 257/767, 438/627, 438/643, 438/927
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor manufacturing method has the steps of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region formed above the insulating film, and an intermediate layer formed between the supporting substrate and the insulating film, forming a semiconductor element in the semiconductor region, and removing the intermediate layer to separate the supporting substrate and the semiconductor region in which the semiconductor element is formed.

Claims

1. A semiconductor device comprising:

a semiconductor region having a semiconductor element; and

a diffusion barrier layer provided in the semiconductor region and being shaped like a bowl,

wherein the diffusion barrier layer is proved in a region containing a plurality of chip regions.

2. A semiconductor device comprising:

a semiconductor region having a semiconductor element; and

a diffusion barrier layer provided in the semiconductor region and being shaped like a bowl,

wherein the diffusion barrier layer is provided in each of a plurality of chip regions.

3. A semiconductor device comprising:

a supporting substrate;

an insulating film provided on the supporting substrate;

a semiconductor region provided on the insulating film, the semiconductor region having a semiconductor element formed therein; and

a diffusion barrier layer a part of which is provided in the semiconductor region, a part of which is provided in the insulating film, a bottom of which is placed in the supporting substrate and being shaped like a bowl,

wherein the diffusion barrier layer is provide in a region containing a plurality of chip regions.

4. A semiconductor device comprising:

a supporting substrate;

a insulating film provided on the supporting substrate;

a semiconductor region provided on the insulating film, the semiconductor region having a semiconductor element formed therein; and

a diffusion barrier layer a part of which is provided in the semiconductor region, a part of which is provided in the insulating film, a bottom of which is placed in the supporting substrate and being shaped like a bowl,

wherein the diffusion barrier layer is provided in each of a plurality of chip regions.