Method and apparatus for a dense metal programmable ROM

• US 6,542,396 B1
• Filed: 09/29/2000
• Issued: 04/01/2003
• Est. Priority Date: 09/29/2000
• Status: Expired due to Term

• Current Assignee: Arm Incorporated (SoftBank Group Corp.)
• Original Assignee: Artisan Components, Inc. (SoftBank Group Corp.)
• Inventors: Becker, Scott T.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/675,574
• Time in Patent Office: 914 Days
• Field of Search: 365/63, 365/51, 365/94, 365/104
• US Class Current: 365/94
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/34 Source electrode or drain electrode programmed

Abstract

A metal programmable ROM is disclosed that includes a memory cell array having a depth that is defined by a plurality of wordlines and a width that is defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and ground, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is included that is defined by a memory cell transistor having its terminals shorted together.

Claims

1. A metal programmable ROM, comprising:

a memory cell array having a depth that is defined by a plurality of wordlines and a width that is defined by a plurality of bitlines;

a group of memory cells coupled between a bitline and ground, each memory cell in the group of memory cells being coupled to at least one other memory cell in the group of memory cells; and

a programmed memory cell defined by a memory cell transistor having a first terminal and second terminal shorted together.

2. A metal programmable ROM as recited in claim 1, wherein each memory cell is coupled to a corresponding wordline in the plurality of wordlines.

3. A metal programmable ROM as recited in claim 2, wherein each memory cell includes a transistor having a first terminal, a second terminal, and gate coupled to a wordline corresponding to the memory cell.

4. A metal programmable ROM as recited in claim 3, wherein a first memory cell of the group of memory cells includes a first transistor having a first terminal and a second terminal, wherein the first terminal is coupled to the bitline.

5. A metal programmable ROM as recited in claim 4, further comprising:

a second memory cell of the group of memory cells, the second memory cell including a second transistor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the first transistor;

a third memory cell of the group of memory cells, the third memory cell including a third transistor having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the second transistor; and

a forth memory cell of the group of memory cells, the fourth memory cell including a fourth transistor having a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to ground.

6. A metal programmable ROM as recited in claim 1, wherein the programmed memory cell is a “

0”

cell.

7. A metal programmable ROM as recited in claim 6, wherein a selected wordline coupled to a memory cell in the group of memory cells is pulled low, and wherein all other wordlines coupled to memory cells in the group of memory cells are asserted high.