Nonvolatile memory and semiconductor device with controlled voltage booster circuit

• US 6,542,411 B2
• Filed: 10/05/2001
• Issued: 04/01/2003
• Est. Priority Date: 10/23/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Kawajiri, Yoshiki, Tanaka, Toshihiro, Fujito, Masamichi, Shinagawa, Yutaka, Tanikawa, Hiroyuki
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/970,675
• Publication Number:
  US 20020048193A1
• Time in Patent Office: 543 Days
• Field of Search: 365/185.33, 365/185.28, 365/185.29, 365/185.3, 365/189.09, 365/218, 365/226
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3472 Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Abstract

A nonvolatile memory includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.

Claims

1. A nonvolatile memory comprising:

a memory array having a plurality of nonvolatile memory elements which store data according to magnitudes of threshold voltages thereof;

a booster circuit which generates a voltage applied to each of the nonvolatile memory elements upon writing or erasing of the data;

a boosted voltage detecting circuit which detects the level of the voltage boosted by the booster circuit;

a write/erase control circuit which starts the writing or erasing based on the detection of the voltage by the boosted voltage detecting circuit;

a write/erase end detecting circuit which detects the completion of the writing or erasing started by the write/erase control circuit; and

an end flag indicative of the completion of the writing or erasing started by the write/erase control circuit;

further including a control register having control bits each indicative of an entry into an operation for the writing or erasing,

wherein the booster circuit starts boosting according to the control bit set thereto.

2. The nonvolatile memory according to claim 1, further including,

a plurality of booster circuits which generate a plurality of voltages respectively applied to the nonvolatile memory elements upon writing or erasing of data; and

a plurality of boosted voltage detecting circuits which respectively detect the levels of the voltages boosted by the plurality of booster circuits,

wherein the write/erase control circuit starts writing or erasing based on the result that the plurality of boosted voltage detecting circuits have detected that all the boosted voltages respectively have attained a predetermined level.

3. The nonvolatile memory according to claim 2, wherein the write/erase end detecting circuit comprises a delay circuit which delays a signal detected by said each boosted voltage detecting circuit, or a counter circuit which counts a clock signal, based on the detected signal.

4. The nonvolatile memory according to claim 3, further including a discharge circuit which discharges the voltage boosted by the booster circuit,

wherein the discharge circuit starts discharging based on a signal detected by the write/erase end detecting circuit.

5. The nonvolatile memory according to claim 4, further including a discharge end detecting circuit which detects that the output voltage of the booster circuit, which has been discharged by the discharge circuit, has reached a predetermined level,

wherein the end flag is set based on a signal detected by the discharge end detecting circuit.

6. The nonvolatile memory according to claim 5, further including a data register which holds write data therein, and a write control circuit which applies a write voltage to each of bit lines according to the write data held in the data register,

wherein when bits for the write data held in the data register are of a logic “

1”

(or logic “

0”

), the write control circuit skips the bits and sequentially applies the write voltage in association with each of bits indicative of the logic “

0”

(or logic “

1”

).

7. The nonvolatile memory according to claim 6, wherein the time required to apply the write voltage is determined based on a clock signal and changed according to a change in the cycle of the clock signal.

8. The nonvolatile memory according to claim 7, further including a shift register which sequentially outputs the write voltage, based on the clock signal and the write data held in the data register,

wherein the write/erase end detecting circuit detects that a pulse has reached a final stage of the shift register, thereby judging the writing to be completed.

9. The nonvolatile memory according to claim 8, further including a level shifter which supplies the boosted voltage generated by the booster circuit to each of the nonvolatile memory elements upon writing or erasing, and a level determining circuit which determines the level of the boosted voltage generated by the booster circuit,

wherein when the level determining circuit has determined that the boosted voltage has exceeded a predetermined level, the level determining circuit serves so as to select a source voltage applied to the level shifter.

10. The nonvolatile memory according to claim 9, further including a second level determining circuit which determines the level of the boosted voltage generated by the booster circuit,

wherein the booster circuit comprises a charge pump comprised of MOSFETs, which are formed in a plurality of well regions formed on the surface of a semiconductor substrate in the form of being divided into the high-voltage side and the low-voltage side, and the booster circuit is configured so as to select a bias voltage applied to the well region on the high-voltage side when the second level determining circuit determines that the boosted voltage has reached a predetermined level.

11. The nonvolatile memory according to claim 10, further including a command register which holds a command code supplied from outside, and a sequence control circuit which performs write or erase control according to the command code set to the command register,

wherein the sequence control circuit sets the respective control bits of the control register in response to a predetermined signal outputted from an internal circuit and starts the operations of other internal circuits to which the control bits are set.

12. A semiconductor device incorporating therein:

a nonvolatile memory having a plurality of nonvolatile memory elements which store data according to the magnitudes of threshold voltages thereof;

a booster circuit which generates a voltage applied to each of the nonvolatile memory elements upon writing or erasing of the data;

a boosted voltage detecting circuit which detects the level of the voltage boosted by the booster circuit;

a write/erase control circuit which starts the writing or erasing based on the detection of the voltage by the boosted voltage detecting circuit;

a write/erase end detecting circuit which detects the completion of the writing or erasing started by the write/erase control circuit;

an end flag indicative of the completion of the writing or erasing started by the write/erase control circuit;

a control register having control bits each indicative of an entry into an operation for the writing or erasing; and

a control circuit for giving instructions as to any of the writing, erasing and reading to the nonvolatile memory according to the setting of the control bits of the control register.

13. The semiconductor device according to claim 12, wherein the control circuit reads the end flag to thereby detect that the operation for the nonvolatile memory has been completed, and sets the corresponding control bit of the control register to thereby provide the following instructions.

14. The semiconductor device according to claim 13, further including a plurality of booster circuits which generate a plurality of voltages applied to the nonvolatile memory elements upon writing and erasing of data;

and

a plurality of boosted voltage detecting circuits which respectively detect the levels of the voltages boosted by the plurality of booster circuits,

wherein the write/erase control circuit starts writing or erasing based on the result that the plurality of boosted voltage detecting circuits have detected that all the boosted voltages respectively have attained a predetermined level.

15. The semiconductor device according to claim 14, wherein the write/erase end detecting circuit comprises a delay circuit which delays a signal detected by said each boosted voltage detecting circuit, or a counter circuit which counts a clock signal, based on the detected signal.

16. The semiconductor device according to claim 15, further including a discharge circuit which discharges the voltage boosted by the booster circuit,

wherein the discharge circuit starts discharging based on a signal detected by the write/erase end detecting circuit.

17. The semiconductor device according to claim 16, further including a discharge end detecting circuit which detects that the output voltage of the booster circuit, which has been discharged by the discharge circuit, has reached a predetermined level,

wherein the end flag is set based on a signal detected by the discharge end detecting circuit.

18. The semiconductor device according to claim 17, further including a data register which holds write data therein, and a write control circuit which applies a write voltage to each of bit lines according to the write data held in the data register,

wherein when bits for the write data held in the data register are of a logic “

1”

(or logic “

0”

), the write control circuit skips the bits and sequentially applies the write voltage in association with each of bits indicative of the logic “

0”

(or logic “

1”

).

19. The semiconductor device according to claim 18, wherein the time required to apply the write voltage is determined based on a clock signal and changed according to a change in the cycle of the clock signal.

20. The semiconductor device according to claim 18, further including a shift register which sequentially outputs the write voltage, based on the clock signal and the write data held in the data register,

wherein the write/erase end detecting circuit detects that a pulse has reached a final stage of the shift register, thereby judging the writing to be completed.

21. The semiconductor device according to claim 20, further including a level shifter which supplies the boosted voltage generated by the booster circuit to each of the nonvolatile memory elements upon writing or erasing, and a level determining circuit which determines the level of the boosted voltage generated by the booster circuit,

wherein when the level determining circuit has determined that the boosted voltage has exceeded a predetermined level, the level determining circuit serves so as to select a source voltage applied to the level shifter.

22. The semiconductor device according to claim 21, further including a second level determining circuit which determines the level of the boosted voltage generated by the booster circuit,

wherein the booster circuit comprises a charge pump having MOSFETs constituting the charge pump, which are formed in a plurality of well regions formed on the surface of a semiconductor substrate in the form of being divided into the high-voltage side and the low-voltage side, and the booster circuit is configured so as to select a bias voltage applied to the well region on the high-voltage side when the second level determining circuit determines that the boosted voltage has reached a