Satellite payload processing system using polyphase demultiplexing, quadrature phase shift keying demodulation and rate alignment
First Claim
1. A satellite payload processing system for processing an uplink signal consisting of a plurality of single-channel-per-carrier, frequency division multiple access carriers and having an on-board clock, comprising:
- a polyphase demultiplexer processor for separating said uplink signal into a time division multiplexed data stream of symbols and presenting said symbols corresponding to each of said plurality of carriers at respective ones of said frequencies in said uplink signal sequentially to an output of said polyphase demultiplexer processor;
a phase shift keying demodulator connected to said output of said polyphase demultiplexer processor for demodulating said stream of symbols into corresponding time division multiplexed stream of digital baseband bits; and
a rate alignment device for processing said time division multiplexed stream of digital baseband bits to compensate for rate differences between said on-board clock and said symbols corresponding to each of said plurality of carriers received at said satellite, and for demultiplexing said time division multiplexed stream into parallel, rate-aligned channels.
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Abstract
A satellite payload processing system for processing an uplink signal consisting of a plurality of single-channel-per-carrier, frequency division multiple access carriers comprises a polyphase demultiplexer processor for separating the uplink signal into a time division multiplexed data stream of symbols. The polyphase demultiplexer processor presents the symbols corresponding to each of a plurality of carriers at respective ones of the frequencies in the uplink signal sequentially to an output of the polyphase demultiplexer processor. A phase shift keying demodulator and differential decoder demodulates the stream of symbols into corresponding time division multiplexed stream of digital baseband bits, which are then rate-aligned with respect to an on-board clock.
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Citations
7 Claims
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1. A satellite payload processing system for processing an uplink signal consisting of a plurality of single-channel-per-carrier, frequency division multiple access carriers and having an on-board clock, comprising:
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a polyphase demultiplexer processor for separating said uplink signal into a time division multiplexed data stream of symbols and presenting said symbols corresponding to each of said plurality of carriers at respective ones of said frequencies in said uplink signal sequentially to an output of said polyphase demultiplexer processor;
a phase shift keying demodulator connected to said output of said polyphase demultiplexer processor for demodulating said stream of symbols into corresponding time division multiplexed stream of digital baseband bits; and
a rate alignment device for processing said time division multiplexed stream of digital baseband bits to compensate for rate differences between said on-board clock and said symbols corresponding to each of said plurality of carriers received at said satellite, and for demultiplexing said time division multiplexed stream into parallel, rate-aligned channels. - View Dependent Claims (2, 3, 4, 5)
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6. A method of processing an uplink signal consisting of a plurality of single-channel-per-carrier, frequency division multiple access carriers at a satellite having an on-board clock, comprising the steps of:
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separating said uplink signal into a time division multiplexed data stream of symbols and presenting said symbols corresponding to each of said plurality of carriers as respective ones of said frequencies in said uplink signal sequentially for demodulation;
demodulating said stream of symbols into corresponding time division multiplexed stream of digital baseband bits;
compensating for rate differences between said on-board clock and said symbols corresponding to each of said plurality of carriers received at said satellite; and
demultiplexing said time division multiplexed stream into parallel, rate-aligned channels. - View Dependent Claims (7)
determining the timing of said symbols to be characterized as one of lagging behind said on-board clock, leading said on-board clock, and synchronized with respect to said on-board clock; and
performing a respective one of a plurality of rate alignment operations comprising adding at least one bit of predetermined value to said header, removing at least one of said bits and allowing the number of said bits in said header to remain unchanged.
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Specification