Receiving control apparatus and method thereof

• US 6,542,727 B1
• Filed: 08/25/1999
• Issued: 04/01/2003
• Est. Priority Date: 02/19/1999
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kikuchi, Tetsuya
• Primary Examiner(s): Trost, William
• Assistant Examiner(s): Nguyen, Simon
• Application Number:
  US09/383,575
• Time in Patent Office: 1,315 Days
• Field of Search: 455/230, 455/231, 455/343, 455/574, 370/311, 340/7.32, 340/7.33, 340/7.34, 340/7.38, 340/7.39
• US Class Current: 455/343.1
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A time clock oscillator is continually operated to drive an MMI (Man-Machine Interface) unit. Although a TCXO provides a high-accuracy clock signal to accurately receive signals, the power consumption is large. Therefore, during receiving standby only a time clock oscillator is operated, and the TCXO is stopped. Then, timing prior to the reception of signals based on the time clock signal is obtained, and the TCXO is started. Although both the MMI unit and a timing processing unit are driven by the time clock signal before the TCXO is started, after the TCXO is started both a wireless processing unit and the timing process unit are started based on a master clock signal from the TCXO. Then, signals are received based on the master clock signal.

Claims

1. A receiving control apparatus comprising:

reference frequency oscillator generating a high-accuracy first clock signal;

time clock oscillator generating a second clock signal which has a lower accuracy than the clock signal generated by the reference frequency oscillator, with smaller power consumption than the reference frequency oscillator;

receiver receiving transmitted signals;

controller controlling the apparatus, during normal communications so as to drive the receiver and to receive signals based on the first clock signal generated by the reference frequency oscillator, during receiving standby so as to stop the reference frequency oscillator and to manage/control intermittent receiving timing based on the second clock signal generated by the time clock oscillator, when the apparatus shifts from a receiving standby state to a communications state, so as to start the reference frequency oscillator based on the second clock signal generated by the time clock oscillator and after an operation of the reference frequency oscillator is stabilized so as to start reception of signals using the receiver;

frequency deviation detector, after the operation of said reference frequency oscillator is stabilized, detecting frequency deviation against the first clock signal of the second clock signal generated by the time clock oscillator by counting a number of pulses of the first clock signal generated by said reference frequency oscillator in one cycle of a divided clock signal of the second clock signal generated by said time clock oscillator; and

storage storing a frequency deviation value detected by the frequency deviation detector as data, wherein said controller corrects timing for starting said reference frequency oscillator based on the data stored in the storage.

2. The receiving control apparatus according to claim 1, which inserts and deletes a clock pulse for said time clock oscillator generated based on the second clock signal generated by said time clock oscillator at predetermined time intervals based on the data stored in said storage, and corrects a deviation in time indication generated by a counting signal of said time clock oscillator.

3. The receiving control apparatus according to claim 1, further comprising

receiving clock oscillator reproducing a receiving clock signal from received data, wherein when starting said reference frequency oscillator, said controller specifies a phase difference between the receiving clock signal and the second clock signal generated by said time clock oscillator, and controls timing for starting said reference frequency oscillator based on both the phase difference and the data stored in said storage.

4. A receiving control method, comprising the steps of:

(a) generating a first high-accuracy clock signal;

(b) generating a second clock signal which has a lower accuracy than the clock signal generated in step (a), with smaller power consumption than that used in step (a);

(c) receiving transmitted signals;

(d) controlling an apparatus, during normal communications so as to receive signals in step (c) based on the first clock signal generated in step (a), during receiving standby so as to stop generation of clock signals in step (a) and to manage/control intermittent receiving timing based on the second clock signal generated in step (b), when the apparatus shifts from a receiving standby state to a communications state, so as to start a process in step (a) based on the second clock signal generated in step (b) and after an operation in step (a) is stabilized so as to start reception of signals in step (c);

(e) detecting frequency deviation, after the operation in step (a) is stabilized, from the first clock signal of the second clock signal generated in step (b) by counting a number of pulses of the first clock signal generated in step (a) in one cycle of a divided clock signal of the second clock signal generated in step (b); and

(f) storing a frequency deviation value detected in step (e) as data, wherein step (d) corrects timing for starting the process of step (a) based on the data stored in step (f).

5. The receiving control method according to claim 4, which inserts and deletes a clock pulse for said time clock oscillator generated based on the second clock signal generated in step (b) at predetermined time intervals based on the data stored in step (f), and corrects deviation in time indication generated by a counting signal generated in step (b).

6. The receiving control method according to claim 4, further comprising the step of

(g) reproducing a receiving clock signal from received data, wherein when starting the process in step (a), step (c) specifies a phase difference between the receiving clock signal and the second clock signal generated in step (b), and controls timing for starting the process in step (a) based on both the phase difference and the data stored in step (f).