Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits

• US 6,542,844 B1
• Filed: 08/02/2000
• Issued: 04/01/2003
• Est. Priority Date: 08/02/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hanna, Stephen Dale
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Desta, Elias
• Application Number:
  US09/631,130
• Time in Patent Office: 972 Days
• Field of Search: 702/118, 702/119, 702/120, 702/121, 702/122, 702/108, 702/117, 702/123, 702/124, 702/126, 714/39, 714/725
• US Class Current: 702/120
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]

Abstract

A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits provides improved debug and troubleshooting capability for functional logic implemented within field programmable logic arrays (FPGAs). Special test logic configurations may be loaded to enhance the debugging of a system using FPGAs. Registers are used to capture snapshots of internal signals for access by a trace program and a test multiplexer is used to provide real-time output to test pins for use with external test equipment. By retrieving the hardware snapshot information with a trace program running on a system in which the FPGA is used, software and hardware debugging are coordinated, providing a sophisticated model of overall system behavior. Special test circuits are implemented within the test logic configurations to enable detection of various events and errors. Counters are used to capture count values when system processor execution reaches a hardware trace point or when events occur. Comparators are used to detect specific data or address values and event detectors are used to detect particular logic value combinations that occur within the functional logic.

Claims

1. A method for tracing hardware states within a functional logic within a field programmable logic circuit using dynamically reconfigurable test circuits, said method comprising the steps of:

first selecting a test mode from a plurality of test modes for tracing the operation of said functional logic;

after said step of selecting a test mode, second selecting one of a plurality of configurations for said dynamically reconfigurable test circuits in conformity with said selected test mode;

configuring said field programmable logic circuit with said selected configuration to configure said dynamically configurable test circuits;

tracing execution of program code to create a software trace history by executing a test program;

periodically reading a set of registers within said dynamically reconfigurable test circuits to create a hardware trace log in response to the receipt of a hardware trace request during said tracing; and

recording contents of said set of registers in synchronization with said software trace history to produce a full trace history.

2. The method according to claim 1, wherein said step of first selecting a test mode for tracing the operation of said functional logic further selects a format for output of said hardware trace log.

3. The method according to claim 1, wherein said method further comprises the step of detecting an error associated with said functional logic, and wherein said hardware trace request is made in response to said detected error.

4. The method according to claim 1, wherein said dynamically reconfigurable test circuits further comprise counters for counting transitions on internal signals within said functional logic, wherein said method further comprises the step of counting said transitions on internal signals, and wherein said step of periodically reading said set of registers further reads values of said counters.

5. The method according to claim 4, wherein said dynamically reconfigurable test circuits further comprise event detectors for detecting events occurring within said functional logic, wherein said method further comprises the step of detecting events occurring within said functional logic, and wherein said step of periodically reading said set of registers further reads values of said counters to determine the number of counts that have occurred between said events.

6. The method according to claim 5, wherein said event detectors are error detectors for detecting errors occurring within said functional logic and wherein said step of detecting events detects said errors.

7. The method according to claim 1, wherein said step of configuring said field programmable logic circuit includes writing data to said field programmable logic circuit over a peripheral bus.

8. The method according to claim 1, wherein said method further comprises the step selecting a plurality of nodes within said functional logic for output to external test pins on said field programmable logic circuit.

9. A system for controlling an electronic device, said system comprising:

a field programmable logic circuit in which functional logic and a plurality of dynamically reconfigurable test circuits are implemented, wherein said plurality of dynamically reconfigurable test circuits includes a register set;

a processor for executing program instructions to control said electronic device and for instantiating said plurality of dynamically reconfigurable test circuits by loading a selected of a plurality of configuration images into said field programmable logic circuit;

a storage for storing said plurality of configuration images for configuring said field programmable logic circuit and for storing a test program, said test program including;

instructions for tracing execution of program code to create a software trace history;

instructions for periodically reading a set of registers within said plurality of test circuits to create a hardware log in response to the receipt of a hardware trace request; and

instructions for recording the contents of said registers in synchronization with said software trace history to produce a full trace history;

an interconnect coupling said field programmable logic circuit, said processor, and said storage.

10. The system in accordance with claim 9, wherein said processor configures said field programmable logic circuit with a test multiplexor having connections to external pins of said field programmable logic circuit for coupling signals within said functional logic to said external pins for measurement by external test equipment.