Data bus for serial data transmission

• US 6,542,947 B1
• Filed: 09/24/1999
• Issued: 04/01/2003
• Est. Priority Date: 09/24/1998
• Status: Expired due to Fees

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Bühring, Peter
• Primary Examiner(s): Ray, Gopal C.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US09/406,283
• Time in Patent Office: 1,285 Days
• Field of Search: 710/107, 710/104, 710/105-106, 710/110, 710/116, 710/111, 710/123, 710/244, 710/305, 710/306, 710/311, 710/313, 710/62, 710/63, 710/64, 710/72, 709/208, 709/209, 709/217, 709/220, 709/223, 709/225, 370/445, 370/447, 370/449-450, 370/461
• US Class Current: 710/107
• CPC Class Codes: H04L 12/40163 by assigning priority to messages according to a message field
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle

Abstract

A data bus for serial bus transmission between apparatus which are capable of transmitting and/or receiving data via the data bus, recessive and dominant states being present on the data bus and each state being assigned a respective bit value. In order to interrupt a message of low priority by a message of higher priority without incurring a time delay and without additional channels being required, messages are transmitted in message blocks, each message block having at its beginning a start block with (n+k) dominant and j subsequent recessive bits and subsequent data blocks with n data bits and m subsequent recessive bits. A message block of low priority currently being transmitted can be interrupted by another apparatus in order to transmit a message block of higher priority in that the other apparatus generates a new start block on the data bus and subsequently transmits the associated data blocks. An apparatus transmitting a message block via the data bus continuously checks whether a start block appears on the data bus and, if necessary, interrupts the transmission of its message block.

Claims

1. A data bus for serial bus transmission between apparatus which are capable of transmitting and/or receiving data via the data bus, recessive and dominant states being present on the data bus and a respective bit value being associated with each of said states, characterized in that messages are transmitted in message blocks, each message block having at its beginning a start block with (n+k) dominant bits and j subsequent recessive bits and subsequent data blocks with n data bits and m subsequent recessive bits, wherein n, k, j and m are integers greater than zero, and wherein a message block of low priority currently being transmitted can be interrupted by another apparatus in order to transmit a message block of higher priority in that said other apparatus generates a new start block on the data bus and subsequently transmits the associated data blocks, and that an apparatus transmitting a message block on the data bus continuously checks whether a start block appears on the data bus and interrupts the transmission of its data block, if necessary.

2. A data bus as claimed in claim 1, wherein only a defined apparatus is authorized to interrupt other message blocks.

3. A data bus as claimed in claim 1, wherein the type of message with which an apparatus may interrupt other message blocks is defined.

4. A data bus as claimed in claim 1, wherein a transmitting apparatus interrupts the transmission of a message block if the (n+1)^th bit of a data block on the data bus is not recessive.

5. A data bus as claimed in claim 1, wherein a transmitting apparatus interrupts the transmission of a message block when a predetermined number of bits from the (n+1)^th up to including the (n+k)^th bit of a data block on the data bus is/are not recessive.

6. A data bus as claimed in claim 1, wherein a transmitting apparatus bit by bit checks an own message block on the bus during the transmission and interrupts this message block when a bit which is transmitted as a recessive bit actually appears as a dominant bit on the data bus.

7. A data bus as claimed in claim 1, wherein in order to generate a start block of a message block which interrupts another message block an apparatus possibly utilizes dominant bits present on the data bus.

8. A data bus as claimed in claim 1, wherein a receiver continuously checks whether a new start block of a new second message block appears during a transmitted first message block, and that the receiver possibly interrupts the reception of the transmitted first message block and commences the reception of the second, new message block.

9. A data bus as claimed in claim 1, wherein n=4, m=1, k=1 and j=1.

10. A data bus as claimed in claim 1, wherein there are two priority levels for the message blocks.

11. A data bus as claimed in claim 1, wherein a data error is recognized if no recessive bit appears on the data bus after n data bits and no start block is identified.

12. A data bus as claimed in claim 1, wherein after a start block, transmission of a predetermined number of recessive or dominant bits takes place, in dependence on the priority of the message block to be transmitted.

13. A data bus as claimed in 1, wherein said data bus is configured for use in vehicles in order to exchange messages between control apparatus, notably for the immediate transmission of a message block which interrupts other message blocks and ignites an airbag of the vehicle.

14. A data bus for serial data transmission between apparatus which are capable of transmitting and receiving data via the data bus, comprising:

recessive and dominant states on the data bus, wherein each of the states have a respective bit value associated therewith;

wherein messages are transmitted in message blocks, wherein each message block commences with a start block that includes (n+k) dominant bits and j subsequent recessive bits and that is followed by a data block that includes n data bits and m recessive bits, and wherein n, k, j and m are integers greater than zero;

wherein a message block of low priority currently being transmitted can be interrupted by another apparatus in order to transmit a message block of higher priority, wherein the other apparatus generates a new start block on the data bus and subsequently transmits the associated data blocks, wherein an apparatus transmitting a message block on the data bus continuously checks whether a start block appears on the data bus and interrupts the transmission of its data block, if necessary, and wherein a receiver continuously checks whether a new start block of a new second message appears during a transmitted first message block, and that the receiver possible interrupts the reception of the transmitted first message block and commences reception of the second, new message block.