Event counter

• US 6,542,985 B1
• Filed: 09/23/1999
• Issued: 04/01/2003
• Est. Priority Date: 09/23/1999
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Johnson, David C., Fuller, Douglas A.
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/404,684
• Time in Patent Office: 1,286 Days
• Field of Search: 714/35, 714/38, 714/39, 714/47, 714/244, 714/10, 709/319, 709/107, 709/224, 709/102, 713/502, 713/501, 712/227, 712/224, 712/228, 712/244, 712/217, 712/245, 712/223, 712/230, 712/243, 712/226, 712/231, 711/211, 711/217, 711/219, 710/262, 710/29, 710/117, 710/41, 710/124, 710/130, 710/131
• US Class Current: 712/217
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 9/223 Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

A data processor is disclosed that executes a number of microcode instruction words. Each of the microcode instruction words has a bit field reserved to indicate which, if any, event counters are to be incremented. This enables the number of executions of a particular microcode instruction word to be counted. By simply changing the microcode bits in the bit fields of the microcode instruction words, the event counter can be programmed to count any number or pattern of microcode instruction word executions. In one embodiment, there is a one-to-one correspondence between each bit in the bit field and each event counter. In another system, the bits in the bit field are decoded to provide an address that selects selected event counters.

Claims

1. In a microcode instruction processor having a microcode instruction register for storing a microcode instruction, the microcode instruction coupled to a control unit, for counting the number of times the microcode instruction of said selected microcode instructions are executed in a computer, wherein the improvement comprises:

means for indicating whether to count execution of the microcode instruction of all said selected microcode instructions;

means for counting execution of the microcode instruction when said indicating means indicates that the microcode instruction is to be counted; and

means for incrementing a counter each time a microcode instruction is executed that has a one bit field that indicates the corresponding microcode instruction should be counted.

2. In a microcode instruction processor as recited in claim 1, wherein said indicating means includes a bit field in said microcode instruction that indicates whether to count execution of said microcode instruction.

3. In a microcode instruction processor as recited in claim 2, wherein said bit field is a single bit and said counting means includes a single counter for counting said indicated microinstructions.

4. In a microcode instruction processor as recited in claim 2, wherein said bit field has more than one bit.

5. In a microcode instruction processor as recited in claim 4, wherein said counting means includes a number of microcode instruction counters equal in number to said number of bits in said bit field, such that each bit corresponds to one of the microcode instruction counters.

6. In a microcode instruction processor as recited in claim 4, wherein said counting means includes:

a number of microcode instruction counters that is greater than said number of bits in said bit field; and

a microcode instruction counter decoder for receiving the number of bits and for providing a decode address of the bits to the number of microcode instruction counters.

7. In a microcode instruction processor as recited in claim 6, further comprising an address generator for receiving an input based at least in part on a machine instruction and for outputting an address into a microcode instruction storage device for providing the microcode instruction.

8. In a microcode instruction processor as recited in claim 7, wherein said address generator is addressable and receives an address, further comprising a translation table for receiving at least a portion of said machine instruction and for outputting said address to said address generator for generating an address into said microcode instruction storage device.

9. In a microcode instruction processor as recited in claim 8, further comprising a plurality of external signal paths operably coupled to the address generator, wherein the address generator output is based at least in part on said external signal values.

10. A system for counting the execution of selected microinstructions in a computer comprising:

an addressable memory device storing microcode instruction words having an event counter bit field with more than one bit for designating an event counter selection;

a microcode instruction word register for receiving an addressed microcode instruction word from said addressable memory device;

a decoder for decoding a portion of said microcode instruction word register corresponding to said event counter bit field and for outputting an event counter selection; and

a plurality of event counters operably coupled to said decode, each of the plurality of event counters incrementing when selected by said event counter selection.

11. A system for counting selected microinstruction executions as recited in claim 10, further comprising:

a plurality of readout registers coupled to said event counters for reading said event counter values and storing said event counter values.

12. A system for counting selected microinstruction executions as recited in claim 11, further comprising a plurality of readout paths coupled to said readout registers for reading the values of said read out registers.

13. A system for counting the execution of selected microcode instruction words in a computer as recited in claim 12, wherein said decoder selects one event counter for each bit set in said bit field, such that more than one event counter can be incremented for each microcode instruction.

14. A system for counting the execution of selected microcode instruction words in a computer as recited in claim 12, wherein said decoder decodes said bit field as a base two number and selects at most one of said event counters based on said base two value.

15. A method for counting the number of times selected microcode instruction words are executed in a computer, the method comprising the steps of:

providing an instruction processor including;

at least one event counter for counting events, each of the at least one event counters having an input for incrementing said event counter and an output for reading said event counter contents; and

a microcode instruction storage means for storing a number of microcode instructions, the microcode storage means having at least one bit field for each microcode instruction that indicates which if any of said at least one event counters are to be incremented when the corresponding microcode instruction is executed, said microcode instruction storage means being operably coupled to the inputs of said event counters;

setting bits in said microcode instruction storage means bit fields for those microcode instructions for which counting is desired;

executing selected microcode instructions;

sequentially providing the at least one bit field that corresponds to each executed microcode instruction the inputs of said event counters, causing those event counters that correspond to the set bits in the at least one bit field to increment; and

reading out said event counter contents from said event counters.

16. A method as recited in claim 15, wherein said microcode instruction bit field contains a number of bit positions greater than one and have a one-to-one correspondence to said event counters, such that setting a bit in the bit field causes said corresponding event counter to be incremented when the corresponding microinstruction is executed.

17. A method as recited in claim 15, wherein there are more event counters than there are bits in the bit fields, the method further comprising the step of:

decoding the bits in the bit field into an address that selects one or more event counters and causes the selected event counters to increment.

18. A method as recited in claim 17, wherein the number of bits in each bit field is three, and the number of event counters is seven.

19. A method as recited in claim 17, wherein said bit fields are encoded as a base 2 number for selecting the selected event counters.

20. A method for counting the number of times selected microcode instructions are executed in a computer, the method comprising the steps of:

providing a bit field for each microcode instruction, wherein the bit field identifies whether the corresponding microcode instruction should be counted;

executing selected microcode instructions on the computer; and

incrementing a counter each time a microcode instruction is executed that has a one bit field that indicates the corresponding microcode instruction should be counted.

21. A method for counting microcode instruction executions as recited in claim 20, wherein said bit field identifies at least one of a number of counters.

22. A method for counting microcode instruction executions as recited in claim 21, wherein said incrementing step increments all counters identified by the bit field.