Electronic chip package

• US 6,544,638 B2
• Filed: 09/10/2001
• Issued: 04/08/2003
• Est. Priority Date: 11/08/1996
• Status: Expired due to Term

• Current Assignee: W. L. Gore & Associates (W.L. Gore & Associates)
• Original Assignee: Gore Enterprise Holdings Incorporated (W.L. Gore and Associates)
• Inventors: Korleski, Joseph E., Fischer, Paul J.
• Primary Examiner(s): LAM, CATHY FONG FONG
• Application Number:
  US09/950,131
• Publication Number:
  US 20020031650A1
• Time in Patent Office: 575 Days
• Field of Search: 428/322.7, 428/209, 428/901, 428/308.4, 428/317.1, 428/325, 428/344, 428/421, 174/255, 174/258, 174/259, 257/702, 257/703, 257/705, 257/729
• US Class Current: 428/322.7
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49883 the conductive materials containing organic materials or pastes, e.g. for thick films for printed circuits H05K1/092
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0353 consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
• CPC Class Codes: H05K 3/022 Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
• CPC Class Codes: Y10S 428/901 Printed circuit
• CPC Class Codes: Y10T 428/24917 including metal layer
• CPC Class Codes: Y10T 428/249958 Void-containing component is synthetic resin or natural rubbers
• CPC Class Codes: Y10T 428/249982 With component specified as adhesive or bonding agent
• CPC Class Codes: Y10T 428/249999 Differentially filled foam, filled plural layers, or filled layer with coat of filling material
• CPC Class Codes: Y10T 428/252 : Glass or ceramic [i.e., fired or glazed clay, cement, etc.] [porcelain, quartz, etc.]
• CPC Class Codes: Y10T 428/2804 : Next to metal
• CPC Class Codes: Y10T 428/3154 : Of fluorinated addition polymer from unsaturated monomers

Abstract

An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature T_g greater than 200° C. and a volumetric coefficient of thermal expansion of ≦75 ppm/° C. A semiconductor device is electrically attached to the laminated substrate.

Claims

1. A chip package comprising:

a laminated substrate having at least one conductive layer; and

at least one dielectric layer bonded to the conductive layer, the dielectric layer having a glass transition temperature T_g greater than 200°

C. and a volumetric coefficient of thermal expansion of ≦

75 ppm/°

C.; and

the dielectric layer is a thermoset adhesive having an inorganic filler material disposed therein; and

a semiconductor device electrically attached to the laminated substrate.

2. The chip package according to claim 1, wherein the at least one conductive layer and the at least one dielectric layer are bonded together so that the thickness of the laminated substrate is between about 5 mils and about 20 mils thick, inclusive.

3. The chip package according to claim 1, wherein the dielectric layer is selected from the group consisting of:

polyimides, polyimide laminates and epoxy resins.

4. The chip package according to claim 1, wherein the dielectric layer is an expanded organic material having an inorganic filler material.

5. The chip package according to claim 4, wherein the expanded organic material is a fluoropolymer matrix.

6. The chip package according to claim 4, wherein the fluoropolymer matrix is formed from the group consisting of:

polytetrafluoroethylene and expanded polytetrafluoroethylene.

7. The chip package according to claim 1, wherein the dielectric layer further includes a resin selected from the group consisting of:

a blend of cyanate ester and epoxy, a bismaleimide resin, benzocyclobutene resin, and a polyimide.

10. The chip package according to claim 1, 8, or 9, wherein the semiconductor device has a first coefficient of thermal expansion α

₁, and

wherein the laminated substrate has a second coefficient of thermal expansion α

₂, the second coefficient of thermal expansion α

₂ being different from the first coefficient of thermal expansion α

₁ by ≦

20 ppm.

11. The chip package according to claim 1, 8, or 9, wherein the semiconductor device has a first coefficient of thermal expansion α

₁, and

wherein the laminated substrate has a second coefficient of thermal expansion α

₂, wherein the second coefficient of thermal expansion α

₂ is nominally 15 ppm different from the first coefficient of thermal expansion α

₁.

8. A chip package comprising:

a laminated substrate having at least one conductive layer and at least one dielectric layer bonded to the conductive layer, wherein the dielectric layer includes a thermoset adhesive having an inorganic filler, and wherein the dielectric layer has a glass transition temperature (T_g) greater than 200°

C. and a volumetric coefficient of thermal expansion of ≦

75 ppm/°

C.; and

a semiconductor device electrically attached to the laminated substrate.

12. The chip package according to claim 8 or 9, wherein the at least one conductive layer and the at least one dielectric layer are bonded together so that the thickness of the laminated substrate is between about 5 mils and about 20 mils thick, inclusive.

9. A chip package comprising:

a laminated substrate having at least one conductive layer and at least one dielectric layer bonded to the conductive layer, wherein the dielectric layer includes a thermoset adhesive, an organic resin and an inorganic filler which is a particulate, and wherein the dielectric layer has a glass transition temperature (T_g) greater than 200°

C.; and

a semiconductor device electrically attached to the laminated substrate.