SOI stacked DRAM logic

• US 6,544,837 B1
• Filed: 03/17/2000
• Issued: 04/08/2003
• Est. Priority Date: 03/17/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ma, William H.-L., Divakauni, Ramachandra, Hakey, Mark C., Tonti, William R., Mandelman, Jack A.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Brewster, William M.
• Application Number:
  US09/527,743
• Time in Patent Office: 1,117 Days
• Field of Search: 438/455, 438/456, 438/459, 438/243
• US Class Current: 438/243
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor
• CPC Class Codes: Y10S 977/712 formed from plural layers of nanosized material, e.g. stacked structures
• CPC Class Codes: Y10S 977/721 On a silicon substrate
• CPC Class Codes: Y10S 977/779 Possessing nanosized particles, powders, flakes, or clusters other than simple atomic impurity doping
• CPC Class Codes: Y10S 977/90 having step or means utilizing mechanical or thermal property, e.g. pressure, heat
• CPC Class Codes: Y10S 977/94 in a logic circuit

Abstract

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

Claims

1. A method of forming a semiconductor integrated circuit, comprising the steps of:

forming an oxide layer on a first wafer;

forming trenches through said oxide layer and extending into said first wafer;

forming an insulator within a said trench;

filling said trenches with a conductive material;

bonding a second wafer to said oxide layer;

forming integrated circuit elements of a second type at a surface of said second wafer directly; and

forming connections from said integrated circuit elements of a second type in said second wafer to said conductive material in a trench in said first wafer.

2. A method as recited in claim 1, wherein said second wafer is formed by the steps of:

implanting hydrogen in said first wafer from a first surface;

forming an oxide on said first surface of said first wafer; and

cleaving said second wafer from said first wafer at a location of hydrogen implanted therein prior to said step of forming integrated circuit elements in said first wafer.

3. A method as recited in claim 2, including a step of polishing a surface of said second wafer cleaved from said first wafer.

4. A method as recited in claim 1, further including a step of testing or burn-in of circuit elements formed in said first wafer prior to said bonding step.

5. A method as recited in claim 1, further including a step of testing or burn-in of circuit elements formed at a surface of said second wafer prior to said bonding step.

6. A method as recited in claim 4, further including a step of testing or burn-in of circuit elements formed at a surface of said second wafer prior to said bonding step.

7. A method as recited in claim 1, including the further step of connecting selected circuit elements formed in said first wafer in parallel.

8. A method as recited in claim 1, wherein said step of forming connections is defined lithographically.

9. A method as recited in claim 8, wherein some of said connections to said first wafer are formed at a pitch similar to intrachip connections between circuit elements formed at a surface of said second wafer.

11. A method as recited in claim 1 wherein said step of forming an insulator comprises growing an oxide.

10. A method of providing power to logic circuits formed on an SOI wafer, said method including steps of:

forming an oxide layer on a bulk silicon wafer;

forming trenches through said oxide layer and extending into said first wafer;

forming an insulator within a said trench;

filling said trenches with a conductive material;

bonding said SOI wafer directly to said oxide layer on said bulk silicon wafer; and

forming lithographically defined connections between said conductive material in a trench and circuit elements on said SOI wafer.

12. A method as recited in claim 10 wherein said step of forming an insulator comprises growing an oxide.