Pocket mounted chip having microstrip line

• US 6,545,227 B2
• Filed: 07/11/2001
• Issued: 04/08/2003
• Est. Priority Date: 07/11/2001
• Status: Expired due to Fees

• Current Assignee: Mce/Kdi Corporation
• Original Assignee: Mce/Kdi Corporation
• Inventors: Silverman, Lawrence H.
• Primary Examiner(s): Paladini, Albert W.
• Assistant Examiner(s): ALCALA, JOSE H
• Application Number:
  US09/903,292
• Publication Number:
  US 20030012006A1
• Time in Patent Office: 636 Days
• Field of Search: 174/260, 361/772, 361/776, 361/779, 361/780, 361/783, 361/792, 361/793, 361/794, 361/795, 361/774, 257/723, 257/724, 257/784
• US Class Current: 174/260
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/1903 : including wave guides

Abstract

An integrated circuit device includes a semiconductor chip, a circuit board and a layer of bonding material. The semiconductor chip has a metal plated surface on a first side and has a predetermined thickness. A first conductive layer formed of electrically conductive material is bonded to a first side of a first dielectric layer and defines a plurality of conducting elements. A second conductive layer defining a first electrical ground plane and formed of electrically conductive material is bonded to a second side of the first dielectric layer opposite the first conductive layer. The circuit board has a pocket formed therein, passing through the first conductive layer and through the first dielectric layer. The pocket is closed on the second side by the second conductive layer. A portion of the second conductive layer is exposed at a bottom of the pocket. The pocket is of substantially the same size and shape as the semiconductor chip. The pocket receives the semiconductor chip with the first side of the semiconductor chip disposed toward the second conductive layer. A layer of conductive bonding material is disposed in the pocket between the metal plated surface of the semiconductor chip and the second conductive layer. The layer of bonding material mechanically and electrically connects the semiconductor chip to the second conductive layer.

Claims

1. An integrated circuit device comprising:

a semiconductor chip having a contact patch on a first side and having a predetermined thickness;

a microstrip line board having;

a first dielectric layer formed of dielectric material,

a first conductive layer formed of electrically conductive material and bonded to a first side of the first dielectric layer and defining a plurality of conducting elements including a microstrip transmission line,

a second conductive layer defining a first electrical ground plane formed of electrically conductive material and bonded to a second side of the first dielectric layer opposite the first conductive layer, and

the microstrip line board having a pocket formed therein passing through the first conductive layer and through the first dielectric layer and the pocket being open on the first side and being closed on the second side by the second conductive layer and a portion of the second conductive layer being exposed at a bottom of the pocket and the pocket being of substantially the same size and shape as the semiconductor chip and the pocket receiving the semiconductor chip with the first side of the semiconductor chip disposed toward the second conductive layer; and

a layer of bonding material disposed in the pocket between the contact patch of the semiconductor chip and the second conductive layer, and the layer of bonding material mechanically and electrically connecting the semiconductor chip to the second conductive layer.

2. An integrated circuit device as claimed in claim 1 wherein the first dielectric layer has a thickness approximately the same as the predetermined thickness of the semiconductor chip.

3. An integrated circuit device as claimed in claim 1 wherein the microstrip line board further includes:

a second dielectric layer formed of dielectric material,

a third conductive layer formed of electrically conductive material and bonded to a first side of the second dielectric layer and defining a second plurality of conducting elements, and

a fourth conductive layer formed of electrically conductive material and bonded to a second side of the second dielectric layer and defining a second electrical ground plane, and

a third dielectric layer formed of dielectric material disposed between and bonded on a first side to the second conductive layer and bonded on a second side to one of the third conductive layer and the fourth conductive layer.

4. An integrated circuit device as claimed in claim 3 wherein the first dielectric layer is formed of polytetrafluoroethylene.

5. An integrated circuit device as claimed in claim 4 wherein the second dielectric layer is formed of fibers impregnated with a bonding resin.

6. An integrated circuit device as claimed in claim 5 wherein the second dielectric layer is formed of fiberglass reinforced epoxy resin.

7. An integrated circuit device as claimed in claim 6 wherein the third dielectric layer is formed of fibers impregnated with a bonding resin.

8. An integrated circuit device as claimed in claim 1 wherein the portion of the second conductive layer exposed at the bottom of the pocket is gold plated and the contact patch includes a layer of gold.

9. An integrated circuit device as claimed in claim 8 wherein the bonding material is silver filled epoxy.

10. An integrated circuit device comprising:

a semiconductor chip having a gold plated surface on a first side and having a predetermined thickness; and

a microstrip line board having;

a first dielectric layer formed of dielectric material,

a first transmission layer formed of electrically conductive material and bonded to a first side of the first dielectric layer and defining a plurality of conducting elements including a microstrip transmission line and a plurality of adjacent ground lines,

a first ground plane layer formed of electrically conductive material and bonded to a second side of the first dielectric layer and defining a first electrical ground plane and electrically connected to the ground lines by a plurality of vias extending from the first ground plane to the ground lines,

the board having a pocket formed therein passing through the first transmission layer and through the first dielectric layer and the pocket being open on the first side and being closed on the second side by the first ground plane layer and a portion of the ground plane layer being exposed at a bottom of the pocket and the pocket being of substantially the same size and shape as the semiconductor chip and the pocket receiving the semiconductor chip with the first side of the semiconductor chip disposed toward the ground plane layer; and

a layer of bonding material disposed in the pocket between the gold plated surface of the semiconductor chip and the first ground layer and the layer of bonding material mechanically and electrically connecting the semiconductor chip to the first ground layer.

11. An integrated circuit device as claimed in claim 10 wherein the first dielectric layer has a thickness slightly less than a thickness of the semiconductor chip.

12. An integrated circuit device as claimed in claim 10 wherein the microstrip board further includes:

a second dielectric layer formed of dielectric material,

a power and control layer formed of electrically conductive material and bonded to a first side of the second dielectric layer and defining a second plurality of conducting elements, and

a second ground plane layer formed of electrically conductive material and bonded to a second side of the second dielectric layer and defining a second electrical ground plane; and

a third dielectric layer disposed between and bonded to the first ground plane layer and the power and control layer.

13. An integrated circuit device as claimed in claim 12 wherein the first dielectric layer is formed of polytetrafluoroethylene.

14. An integrated circuit device as claimed in claim 13 wherein the second dielectric layer is formed of fibers impregnated with a bonding resin.

15. An integrated circuit device as claimed in claim 14 wherein the second dielectric layer is formed of fiberglass reinforced epoxy resin.

16. An integrated circuit device as claimed in claim 15 wherein the third dielectric layer is formed of fibers impregnated with a bonding resin.

17. An integrated circuit device as claimed in claim 10 wherein a bottom surface of the pocket is gold plated.

18. An integrated circuit device as claimed in claim 17 wherein the bonding material is silver filled epoxy.