Semiconductor device with a plurality of stacked boards and method of making

• US 6,545,228 B2
• Filed: 08/27/2001
• Issued: 04/08/2003
• Est. Priority Date: 09/05/2000
• Status: Active Grant

• Current Assignee: Advanced Interconnect Systems Limited (Vector Capital Corporation)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hashimoto, Nobuaki
• Primary Examiner(s): Talbott, David L.
• Assistant Examiner(s): ALCALA, JOSE H
• Application Number:
  US09/938,515
• Publication Number:
  US 20020027019A1
• Time in Patent Office: 589 Days
• Field of Search: 174/255, 174/262, 174/264, 174/265, 174/266, 174/260, 361/792, 361/793, 361/794, 361/795, 298/30
• US Class Current: 174/260
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: Y10T 29/49126 : Assembling bases

Abstract

A semiconductor device includes a semiconductor chip and a substrate having an interconnecting pattern formed thereover. The substrate has the semiconductor chip mounted on one surface thereof. The substrate has an outline larger than the semiconductor chip. First terminals are formed in a region outside the region of the substrate in which the semiconductor chip is mounted. Second terminals are a part of the interconnecting pattern which exposes its surface opposite to its surface opposing the semiconductor chip in a region closer to a center of the substrate than the first terminals. The semiconductor chip is electrically connected to the first and second terminals.

Claims

1. A semiconductor device comprising:

a semiconductor chip;

a substrate having an interconnecting pattern formed thereover, the substrate having the semiconductor chip mounted on a surface thereof, the substrate having an outline larger than the semiconductor chip;

first terminals formed in a region outside a region of the substrate in which the semiconductor chip is mounted; and

second terminals being a part of the interconnecting pattern which exposes its surface opposite to a surface opposing the semiconductor chip in a region closer to a center of the substrate than the first terminals,

wherein the semiconductor chip is electrically connected to the first and second terminals.

2. The semiconductor device of claim 1, wherein:

the second terminals are formed to be larger in plan form than the first terminals.

3. The semiconductor device of claim 1, wherein:

the pitch of the second terminals is wider than the pitch of the first terminals.

4. The semiconductor device of claim 1, wherein:

the first terminals are formed at an extremity of the substrate and arranged along an edge of the semiconductor chip; and

the second terminals are formed in a region including the region in which the semiconductor chip is mounted.

5. The semiconductor device of claim 1, wherein:

the interconnecting pattern is formed on each of both surfaces of the substrate.

6. The semiconductor device of claim 1, wherein:

the substrate has the interconnecting pattern formed over its surface on which the semiconductor chip is mounted, and the substrate has a plurality of first and second through holes formed therethrough in its portion overlapping with the interconnecting pattern;

the first terminals are positioned over the first through holes; and

the second terminals are provided to be exposed through the second through holes.

7. The semiconductor device of claim 6, wherein:

the first terminals have projections formed to project from a surface of the substrate.

8. The semiconductor device of claim 7, wherein:

the projections of the first terminals are formed with a height exceeding the thickness of the semiconductor chip on the substrate, the projections projecting from either surface of the substrate.

9. The semiconductor device of claim 7, wherein:

the projections of the first terminals are formed to project through the first through holes from a surface of the substrate opposite to a surface on which the semiconductor chip is mounted.

10. The semiconductor device of claim 7, wherein:

the projections of the first terminals are bumps provided so as to be electrically connected to the interconnecting pattern.

11. The semiconductor device of claim 7, wherein:

the first terminals are a part of the interconnecting pattern.

12. The semiconductor device of claim 11, wherein:

the projections of the first terminals are formed by bending a part of the interconnecting pattern in the direction away from a surface of the substrate.

19. A method of manufacture of a semiconductor device comprising the step of testing an electrical characteristics of the semiconductor device of claim 1 through the second terminals which the substrate have.

13. A semiconductor device comprising a plurality of stacked semiconductor devices,

wherein each of the stacked semiconductor devices comprises:

a semiconductor chip;

a substrate having an interconnecting pattern formed thereover, the substrate having the semiconductor chip mounted on a surface thereof, the substrate having an outline larger than the semiconductor chip;

first terminals formed in a region outside a region of the substrate in which the semiconductor chip is mounted; and

second terminals being a part of the interconnecting pattern which exposes its surface opposite to a surface opposing the semiconductor chip in a region closer to a center of the substrate than the first terminals,

wherein the semiconductor chip is electrically connected to the first and second terminals,

wherein the semiconductor chips in upper and lower ones of the stacked semiconductor devices are electrically connected.

14. The semiconductor device of claim 13, further comprising:

external terminals, the substrate of the lowest one of the stacked semiconductor devices having the external terminals, the external terminals projecting from a surface of the substrate opposite to a surface opposing the substrate of another of the stacked semiconductor devices.

15. The semiconductor device of claim 14, wherein:

the external terminals are formed by bending a part of the interconnecting pattern including the second terminals in the direction away from a surface of the substrate.

16. The semiconductor device of claim 15, wherein:

the external terminals are provided so as to be electrically connected to the second terminals.

17. A circuit board having the semiconductor device of claim 13 mounted thereon, the circuit board electrically connected to the semiconductor device by the second terminals which the substrate of the lowest one of the stacked semiconductor devices have.

18. An electronic instrument having the semiconductor device of claim 13.

20. A method of manufacture of a semiconductor device comprising the step of testing an electrical characteristics of the semiconductor device of claim 13 through the second terminals which the substrate of the lowest one of the stacked semiconductor devices have.