Thin film transistor flat display

• US 6,545,293 B2
• Filed: 06/07/2001
• Issued: 04/08/2003
• Est. Priority Date: 09/30/2000
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Wong, Jia-Fam
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Sefer, Ahmed N.
• Application Number:
  US09/876,730
• Publication Number:
  US 20020038893A1
• Time in Patent Office: 670 Days
• Field of Search: 257/59, 257/72, 257/347, 257/359, 349/42, 349/43
• US Class Current: 257/59
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

The thin film transistor (TFT) display includes a gate electrode and a gate pad respectively formed on a transistor area and a bonding pad area, an insulating layer covered over the gate electrode and a first area of the gate pad, a first semiconductor layer covered over the insulating layer, a second semiconductor layer covered over a predetermined area of the first semiconductor layer, and a metal layer covered on the second semiconductor layer to form a source electrode and a drain electrode. A channel is formed between the source and drain electrodes. The TFT display further includes a first conductive layer, a protective layer, and a second conductive layer. The first conductive layer is formed on the drain electrode, the source electrode, and the substrate except for the surface of the gate pad. The protective layer covers the first conductive layer and the first area of the gate pad. The second conductive layer is formed on the area uncovered by the protective layer, the second conductive is connected to the first conductive layer for electrically connect the gate pad and the metal layer.

Claims

1. A thin film transistor (TFT) display, comprising:

a substrate having at least a transistor area and a bonding pad area;

a gate electrode and a gate pad respectively formed on the transistor area and the bonding pad area, the gate pad having a first area and a second area;

an insulating layer formed on the substrate to cover the gate electrode and the-first area of the gate pad;

a first semiconductor layer covering the insulating layer;

a second semiconductor layer covering a predetermined area of the first semiconductor layer;

a metal layer covering the second semiconductor layer to form a source electrode and a drain electrode, a channel being formed between the source and the drain electrodes;

a first conductive layer formed on the surface of the drain electrode, the source electrode, and the substrate except for the surface of the gate pad;

a protective layer formed on the transistor area and the bonding pad area, the protective layer filled into the channel and covering the first conductive layer above the source electrode and the drain electrode, and the first area of the gate pad; and

a second conductive layer formed on the area uncovered by the protective layer and the second area of the gate pad, the second conductive layer connected with the first conductive layer for electrically connecting the gate pad and the metal layer, wherein

the second conductive layer covers the second area of the gate pad and the first conductive layer on the transistor area, and the first conductive layer covers the surface and sidewall of the metal layer on the transistor area so that the gate pad is electrically connected to the metal layer by the first and the second conductive layers.

2. The TFT display as claimed in claim 1, wherein the substrate further comprises a gate line, and the end of the gate line is the gate pad.

3. The TFT display as claimed in claim 2, wherein the substrate further comprises a signal line being perpendicular to the gate line and formed by the metal layer, and a signal pad is formed at the end of the signal line.

4. The TFT panel display as claimed in claim 3, wherein the second conductive layer covers the gate pad and the signal pad to electrically connect the gate line and the signal line.

5. The TFT display as claimed in claim 1, wherein the first and the second conductive layers are made of indium tin oxide (ITO).

6. The TFT display as claimed in claim 1, wherein the first semiconductor layer is made of amorphous silicon (a-Si).

7. The TFT display as claimed in claim 1, wherein the second semiconductor layer is made of n⁺ doped silicon.