Linear capacitor and process for making same

• US 6,545,305 B1
• Filed: 04/14/2000
• Issued: 04/08/2003
• Est. Priority Date: 05/08/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Randazzo, Todd A.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US09/550,381
• Time in Patent Office: 1,089 Days
• Field of Search: 257/296, 257/306, 257/532, 438/250, 438/253, 438/393, 438/396
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

A capacitor that is a metal to polysilicon capacitor. The capacitor is fabricated by forming a field oxide layer on a substrate. Then, a polysilicon segment is formed on the field oxide layer. This polysilicon segment forms a polysilicon bottom plate for the capacitor. A dielectric layer is formed and planarized. An opening is made in the dielectric layer to expose a portion of the polysilicon segment. Then, an oxide layer is formed on exposed portions of the polysilicon segment. A metal segment is formed on the oxide layer over the opening, wherein the metal segment forms a top-plate for the semiconductor device.

Claims

1. A capacitor in a semiconductor device, comprising:

a substrate;

a field oxide layer formed in the substrate;

a polysilicon segment formed on the oxide layer;

a first dielectric layer formed on the field oxide layer and the polysilicon segment;

a second dielectric layer having a first side and a second side, the first side being substantially in contact with the polysilicon segment and the second side being in contact with a top-plate of the capacitor; and

a contact to the portion of the polysilicon segment out of contact with the second dielectric layer.

2. The capacitor claim 1, wherein the field oxide layer has a thickness from about 2000 Angstroms to about 7000 Angstroms.

3. The capacitor claim 1, wherein the polysilicon segment has a thickness from about 1200 Angstroms to about 4000 Angstroms.

4. The capacitor claim 1, wherein the second dielectric layer has a thickness from about 100 Angstroms to about 400 Angstroms.

5. The capacitor claim 1, wherein the first dielectric layer has a thickness from about 3000 Angstroms to about 13000 Angstroms.

6. The capacitor claim 1, wherein the second dielectric layer is an oxide nitride oxide stack.

7. The capacitor of claim 1, further comprising a metal segment on the second dielectric layer over the opening, wherein the metal segment forms a top-plate for the capacitor and the polysilicon segment forms a bottom-plate for the capacitor.

8. The capacitor claim 7, wherein the metal segment has a thickness from about 100 Angstroms to about 500 Angstroms.

9. The capacitor of claim 1, wherein the capacitor comprises a metal-to-polysilicon capacitor, in and on a silicon substrate, on an integrated circuit having MOSFET.

10. A metal-to-polysilicon capacitor, in and on a silicon substrate, on an integrated circuit having MOSFET devices, comprising:

a field oxide layer on the substrate;

a polysilicon segment on the field oxide layer;

a first dielectric layer on the field oxide layer and the polysilicon segment, wherein an opening is present in the first dielectric layer to expose a portion of the polysilicon segment, which is subjected to doping thereon;

a second dielectric layer having a first side and a second side, the first side being substantially in contact with the polysilicon segment and the second side being in contact with a top-plate of the metal-to-polysilicon capacitor; and

a contact to the portion of the polysilicon segment out of contact with the second dielectric layer,

wherein the polysilicon segment is initially part of a polysilicon layer formed in common with other elements of the integrated circuit.

11. The metal polysilicon capacitor of claim 10, wherein the second dielectric layer being made out of same dielectric material, laid on the polysilicon segment exposed in the opening and on the first dielectric layer wherein a portion of the polysilicon segment is out of contact with the second dielectric layer.

12. The metal polysilicon capacitor of claim 10, further comprising a metal segment on the second dielectric layer over the opening.

13. The metal-to-polysilicon capacitor claim 12, wherein the metal segment has a thickness from about 100 Angstroms to about 500 Angstroms.

14. The metal polysilicon capacitor of claim 12, wherein the metal segment forms a top-plate for the metal-to-polysilicon capacitor and the polysilicon segment forms a bottom-plate for the metal-to-polysilicon capacitor.

15. The metal-to-polysilicon capacitor of claim 10, wherein the contact includes:

a hole in the first dielectric layer to the polysilicon segment;

a metal disposed to being placed into the hole thereby forming a metal plug;

a metal contact on top of the metal plug.

16. The metal-to-polysilicon capacitor of claim 10, wherein the field oxide layer has a thickness from about 2000 Angstroms to about 7000 Angstroms.

17. The metal-to-polysilicon capacitor claim 10, wherein the polysilicon segment has a thickness from about 1200 Angstroms to about 4000 Angstroms.

18. The metal-to-polysilicon capacitor claim 10, wherein the second dielectric layer has a thickness from about 100 Angstroms to about 400 Angstroms.

19. The metal-to-polysilicon capacitor claim 10, wherein the first dielectric layer has a thickness from about 3000 Angstroms to about 13000 Angstroms.

20. The metal-to-polysilicon capacitor claim 10, wherein the second dielectric layer is an oxide nitride oxide stack.