Memory using insulator traps

• US 6,545,314 B2
• Filed: 05/15/2001
• Issued: 04/08/2003
• Est. Priority Date: 11/13/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Geusic, Joseph E.
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Wilson, Scott R.
• Application Number:
  US09/858,304
• Publication Number:
  US 20010038135A1
• Time in Patent Office: 693 Days
• Field of Search: 257/402, 257/405, 257/296, 257/314, 257/317, 257/325, 438/288, 438/217, 438/289, 438/238, 438/239, 438/386, 438/399, 438/260
• US Class Current: 257/325
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 2216/08 Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7888 Transistors programmable by two single electrons
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.

Claims

1. A computer system, the computer system comprising a memory device, the memory device including:

an array of memory cells, at least one of the memory cells including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

2. A memory device, comprising:

an array of memory cells, each memory cell including a transistor in which a gate insulator cries trap sites at a density such that the trap sites arc substantially shielded from each other by intervening portions of the insulator;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuitry coupled to the memory cell array and reading data from memory cells in the array of memory cells.

3. The memory device of claim 2, further comprising a write/erase circuit coupled to the memory cell array and writing data to memory cells in the array of memory cells.

4. The memory device of claim 2, wherein the write/erase circuit stores electrons on the trap sites by hot electron injection.

5. The memory device of claim 2, wherein the write/erase circuit removes electrons from the trap sites by Price-Sat tunneling.

6. The memory device of claim 2, wherein the trap sites are carried in the gate insulator at an real concentration that is approximately between 10¹² and 10¹⁵ trap sites per square centimeter.

7. A memory device comprising:

an array of memory cells, at least one memory cell of which includes a transistor in which a gate insulator carries point defect trap sites at a density such that die trap sites are substantially insulated from each other by intervening portions of the insulator and wherein the trap sites are each capable of capturing no more than one electron;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

8. The memory device of claim 7, wherein the trap sites have an effective cross-sectional area of capture of approximately 10 ⁻

15 cm².

9. The memory device of claim 7, wherein the trap sites have a retention time of approximately between 1 second and 3 million years at a temperature of approximately 85 degrees Celsius.

10. The memory device of claim 7, wherein the trap sites are carried in the insulator at an areal concentration tat is approximately between 10¹² and 10¹⁵ trap sites per square centimeter.

11. The memory device of claim 7, wherein ones of the trap sites do not substantially overlap others of the trap sites.

12. The memory device of claim 7, wherein the insulator is formed on a substrate, and the insulator has a thickness, and the trap sites are carried in the insulator at a distance from the substrate that is approximately ⅓

of a thickness of the insulator.

13. A memory device, comprising:

an array of memory cells, at least one of the memory cells including at least one transistor in which a gate insulator carries trap sites at a density such that the trap sites arc substantially insulated from each other by intervening portions of the insulator and wherein the trap sites have a trapping energy of approximately between 1.3 ev and 2.4 eV;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

14. The memory device of claim 13, wherein the trap sites are carried in the insulator at an areal concentration that is approximately between 10¹² and 10¹⁵ trap sites per square centimeter.

15. The memory device of claim 13, wherein ones of the trap sites do not substantially overlap others of the trap sites.

16. A memory device, comprising:

an array of memory cells, at least one memory cell comprising an insulator carrying trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator, wherein the insulator is selected from a group consisting essentially of amorphous silicon dioxide, quartz, aluminum trioxide, titanium dioxide, lithium niobate, silicon nitride, and diamond;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

17. The memory device of claim 16, wherein the trap sites are carried in the insulator at an areal concentration that is approximately between 10¹² and 10¹⁵ trap sites per square centimeter.

18. The memory device of claim 16, wherein ones of the trap sites do not substantially overlap others of the trap sites.

19. A memory device comprising an insulator carrying point defect trap sites that are electrically isolated from each other by intervening portions of the insulator wherein the trap sites have a trapping energy of between approximately 1.3 eV and approximately 2.4 eV.

20. The memory device of claim 19, wherein the trap sites have a cross-sectional area of capture of approximately 10⁻

15 cm².

21. The memory device of claim 19, wherein the trap sites have a retention time of approximately between 1 second and 3 million years at a temperature of 85 degrees Celsius.

22. The memory device claim 19, wherein the trap sites are carried in the insulator at an areal concentration that is approximately between 10¹² and 10¹⁵ trap sites per square centimeter.

23. The memory device of claim 19, wherein the insulator is formed on a substrate, and the insulator has a thickness, and the trap sites are carried in the insulator at a distance from the substrate that is approximately ⅓

of a thickness of the insulator.

24. A memory device, comprising:

an array of memory cells, at least one memory cell including a transistor in which a gate insulator carries point defect trap sites that are electrically isolated from each other by intervening portions of the insulator wherein the insulator is selected from a group consisting essentially of amorphous silicon dioxide, quartz, aluminum trioxide, titanium dioxide, lithium niobate, silicon nitride, and diamond;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

25. The memory cell of claim 24, wherein the trap sites are carried by the insulator at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator.

26. The memory cell of claim 24, wherein the trap sites are capable of capturing no more than one electron.

27. The memory cell of claim 24, wherein the trap sites have a cross-sectional area of capture of approximately 10⁻

15 cm².

28. A memory device, comprising:

an array of memory cells, at least one of the memory cells including a transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate wherein the floating gate includes point defect trap sites that arc carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the trap sites have a trapping energy of approximately between 1.3 ev and 2.4 ev;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

29. The memory device of claim 28, wherein the trap sites have a retention time of approximately between 1 second and 3 million years at a temperature of 85 degrees Celsius.

30. A memory cell, comprising:

an array of memory cells, at least one of the memory cells including a transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate and wherein the floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the insulator is selected from a group consisting essentially of amorphous silicon dioxide, quartz, aluminum trioxide, titanium dioxide, lithium niobate, silicon nitride, and diamond;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

31. The memory device of claim 30 wherein the trap sites are capable of accepting no more than one electron.

32. A memory device, comprising:

an array of memory cells, at least one memory cell of which includes a transistor, the transistor includes a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate and wherein the floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the insulator has a thickness between the control gate and the channel region, and the point defects are disposed at a distance from the channel region that is approximately ⅓

of the thickness or the insulator;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

33. The memory device of claim 32 wherein the trap sites are capable of capturing no more than one electron.

34. A memory device, comprising:

an array of memory cells, each memory cell including at least one transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate wherein die floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator and wherein the trap sites are carried in the insulator at an areal concentration that is between approximately 10¹² and approximately 10¹⁵ trap sites per square centimeter;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

35. The memory device of claim 34 wherein the trap sites are capable of capturing no more than one electron.

36. A memory cell including a transistor, the transistor including a source, a drain, a channel region between the source and the drain, a control gate and an insulator between the control gate and the channel region, and a floating gate wherein the floating gate includes point defect trap sites that are carried by the insulator at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator.

37. A memory device, comprising:

an array of memory cells, at least one of the memory cells including a transistor, the transistor including a source, a drain, a channel region between the source and drain, a control gate, an insulator between the control gate and the channel region, and a floating gate wherein the floating gate includes point defect trap sites that are carried by the insulator and electrically isolated from each other by intervening portions of the insulator;

addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and

a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.

38. The memory device of claim 37 wherein the insulator of the at least one of the memory cells carries trap sites that arc electrically isolated from each other by intervening portions of the insulator.