MOSFET devices having linear transfer characteristics when operating in velocity saturation mode and methods of forming and operating same

• US 6,545,316 B1
• Filed: 06/23/2000
• Issued: 04/08/2003
• Est. Priority Date: 06/23/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Silicon Wireless Corporation
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US09/602,414
• Time in Patent Office: 1,019 Days
• Field of Search: 257/327-335, 257/341-343, 257/133, 257/139-141, 438/268-274
• US Class Current: 257/329
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate

Abstract

MOSFET embodiments of the present invention provide highly linear transfer characteristics (e.g., I_d v. V_g) and can be used effectively in linear power amplifiers. These linear transfer characteristics are provided by a MOSFET having a channel that operates in a linear mode and a drift region that simultaneously supports large voltages and operates in a current saturation mode. A relatively highly doped transition region is preferably provided between the channel region and the drift region. Upon depletion, this transition region provides a potential barrier that supports separate and simultaneous linear and current saturation modes.

Claims

1. A vertical power device, comprising:

an insulated-gate field effect transistor that utilizes an N-type transition region in a forward on-state current path extending between a source electrode and a drain electrode of the power device in combination with a P-type base region that forms a P-N rectifying junction with the N-type transition region and a trench-based source electrode that extends in a trench having a sidewall that defines an interface with a vertical first conductivity type drift region of the power device, as means for achieving a forward on-state mode of operation in the power device that simultaneously supports linear operation in an inversion-layer channel of the field effect transistor and velocity saturation operation in the drift region when the drain region is positively biased relative to a source region and the P-N rectifying junction is reversed biased to a point where the N-type transition region, which defines a non-rectifying junction with the N-type drift region, is fully depleted by the P-type base region and a maximum voltage at a drain-side of the inversion-layer channel is less than a gate voltage of the insulated-gate field effect transistor.

2. A vertical power device, comprising:

a semiconductor substrate, said semiconductor substrate comprising an N+ substrate region and an N-type drift region that extends on said N+ substrate region and is more lightly doped than said N+ substrate region;

a P-type base region that extends in said semiconductor substrate and defines a first P-N rectifying junction with the N-type drift region;

an N-type transition region that extends in said semiconductor substrate and defines a non-rectifying junction with the N-type drift region and a second P-N rectifying junction with said P-type base region;

an N+ source region that extends in said P-type base region and forms a third P-N rectifying junction with said P-type base region;

an insulated gate electrode that extends on said semiconductor substrate and is positioned opposite said P-type base region so that application of a sufficiently positive gate voltage to said insulated gate electrode causes formation of an inversion-layer channel that extends in said P-type base region and electrically connects said N+ source region to said N-type transition region;

a trench that extends in said semiconductor substrate and has a sidewall that defines an interface with the N-type drift region;

an insulated source electrode in said trench;

a source electrode that is electrically coupled to said N+ source region;

a drain electrode that is electrically coupled to the N+ substrate region; and

wherein said P-type base region is doped at a sufficiently high level and has a sufficient depth in said semiconductor substrate and a length of the inversion-layer channel is sufficiently short that a depletion region formed at the second P-N rectifying junction pinches off said N-type transition region at an operating point when the inversion-layer channel possesses linear behavior and the N-type drift region possesses velocity saturated behavior when a forward on-state current is present in the inversion-layer channel and the N-type drift region.

3. The power device of claim 2, wherein the second P-N rectifying junction pinches off said N-type transition region at a point when a maximum voltage at a drain-side of the inversion-layer channel is less than the positive gate voltage.

4. The power device of claim 3, wherein a maximum N-type doping concentration in said N-type transition region is greater than about ten times an N-type drift region doping concentration at the non-rectifying junction.

5. A vertical power device, comprising:

a semiconductor substrate, said semiconductor substrate comprising an N+ substrate region and an N-type drift region that extends on said N+ substrate region and is more lightly doped than said N+ substrate region;

a P-type base region that extends in said semiconductor substrate and defines a first P-N rectifying junction with the N-type drift region;

an N-type transition region that extends in said semiconductor substrate and defines a non-rectifying junction with the N-type drift region and a second P-N rectifying junction with said P-type base region;

an N+ source region that extends in said P-type base region and forms a third P-N rectifying junction with said P-type base region;

an insulated gate electrode that extends on said semiconductor substrate and is positioned opposite said P-type base region so that application of a sufficiently positive gate voltage to said insulated gate electrode causes formation of an inversion-layer channel that extends in said P-type base region and electrically connects said N+ source region to said N-type transition region;

a source electrode that is electrically coupled to said N+ source region;

a drain electrode that is electrically coupled to the N+ substrate region; and

means, comprising a trench-based insulated source electrode and P-type dopants in said P-type base region, for quickly depleting said N-type transition region in response to increases in a reverse bias across the second P-N rectifying junction so that when the N-type drift region switches from linear behavior to velocity saturated behavior the inversion-layer channel continues to sustain linear behavior and a maximum voltage at a drain side of the inversion layer channel is less than the positive gate voltage.