ESD protection circuit for a semiconductor integrated circuit

• US 6,545,321 B2
• Filed: 03/15/2002
• Issued: 04/08/2003
• Est. Priority Date: 03/19/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Morishita, Yasuyuki
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Farahani, Dana
• Application Number:
  US10/099,708
• Publication Number:
  US 20020130366A1
• Time in Patent Office: 389 Days
• Field of Search: 257/355, 257/356, 257/357, 257/358, 257/359, 257/360, 257/361, 257/362, 257/363, 257/364, 257/365, 257/111, 257/112, 257/119, 257/121, 257/123, 257/124, 257/126, 257/127, 257/173, 257/174, 257/133, 257/134, 257/167, 257/175
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Abstract

When an ESD surge positive against a ground terminal is loaded on the input/output pad, a breakdown current of the n-channel MOS transitor flows via forward-biased diodes consist of a p+ diffusion layer and N well from the input/output pad. As a result, a SCR that comprises a p+ diffusion layer serving as the anodes of the diodes, N well, P well, and n+ diffusion layer serving as the source of the transistor is activated, and then the ESD surge is released to the ground terminal.

Claims

1. An ESD protection circuit for a semiconductor integrated circuit, comprising:

a first-conductivity type semiconductor substrate;

a second-conductivity type well formed in said semiconductor substrate;

a first first-conductivity type diffusion layer, being formed in said second-conductivity type well, that is connected to a pad;

a first second-conductivity type diffusion layer, being formed in said second-conductivity type well;

a second second-conductivity type diffusion layer, formed in a part other than said second-conductivity type well of said semiconductor substrate, that is connected to a reference voltage terminal; and

a trigger device having two terminals in which the one terminal is connected to said first second-conductivity type diffusion layer via wiring and in which the other terminal is connected to a reference voltage terminal, for allowing electric current to flow when a voltage higher than a predetermined value is applied between said two terminals.

2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein said trigger device is a MOS transistor of which a drain is a third second-conductivity type diffusion layer formed in said semiconductor substrate and connected to said first second-conductivity type diffusion layer via said wiring, and of which a source is said second second-conductivity type diffusion layer formed in said semiconductor substrate.

3. The ESD protection circuit for a semiconductor integrated circuit according to claim 2, wherein said second second-conductivity type diffusion layer is located in a region between said second-conductivity type well and said third second-conductivity type diffusion layer.

4. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein said trigger device is a MOS transistor of which a drain is a third second-conductivity type diffusion layer formed in said semiconductor substrate and connected to said first second-conductivity type diffusion layer via said wiring, and of which a source is a forth second-conductivity type diffusion layer formed in said semiconductor substrate and connected to a reference voltage terminal.

5. The ESD protection circuit for a semiconductor integrated circuit according to claim 4, wherein said MOS transistor comprises:

an isolation film formed on a region between said third second-conductivity type diffusion layer and said forth second-conductivity type diffusion layer in said semiconductor substrate;

a gate electrode film formed on said isolation film;

a capacitative element connected between said third second-conductivity type diffusion layer and said gate electrode film; and

a resistive element connected between said gate electrode film and said forth second-conductivity type diffusion layer.

6. The ESD protection circuit for a semiconductor integrated circuit according to claim 4, wherein said MOS transistor comprises:

an isolation film formed on a region between said third second-conductivity type diffusion layer and said forth second-conductivity type diffusion layer in said semiconductor substrate;

a gate electrode film formed on said isolation film;

a capacitative element connected to said third second-conductivity type diffusion layer;

a resistive element connected to said forth second-conductivity type diffusion layer; and

a delay circuit connected between said gate electrode film and the node which is located between the side opposite to the side connected to said third second-conductivity type diffusion layer of said capacitative element and the side opposite to the side connected to said forth second-conductivity type diffusion layer.

7. The ESD protection circuit for a semiconductor integrated circuit according to claim 2, further comprising a diode of which anode is connected to said first second-conductivity type diffusion layer and of which cathode is connected to said third second-conductivity type diffusion layer.

8. The ESD protection circuit for a semiconductor integrated circuit according to claim 7, wherein said diode consists of a plurality of P-N diodes which are cascade connected each other and are formed in a part other than said second-conductivity type well of said semiconductor substrate.

9. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein said first second-conductivity type diffusion layer is connected to a power supply voltage terminal.

10. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein said trigger device is a diode, formed in a part other than said second-conductivity type well of said semiconductor substrate, of which anode is connected to said first second-conductivity type diffusion layer via said wiring and of which cathode is connected to a reference voltage terminal.

11. The ESD protection circuit for a semiconductor integrated circuit according to claim 10, wherein said diode consists of a plurality of P-N diodes which are cascade connected each other and are formed in a part other than said second-conductivity type well of said semiconductor substrate.

12. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein a distance between said first first-conductivity type diffusion layer and an end face of said second-conductivity type well, the end face being located in a region between said first first-conductivity type diffusion layer and said second second-conductivity type diffusion layer, is smaller than a depth of said second-conductivity type well.

13. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, further comprising a first-conductivity type well formed adjacent to said second-conductivity type well in said first-conductivity type semiconductor substrate.

14. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, further comprising a diode of which cathode is connected to said first first-conductivity type diffusion layer and of which anode is connected to a reference voltage terminal.

15. The ESD protection Circuit for a semiconductor integrated circuit according to claim 1, wherein said pad is connected to an external input terminal, an external output terminal or a power supply voltage terminal.

16. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, further comprising a second first-conductivity type diffusion layer formed in a part other than said second-conductivity type well of said semiconductor substrate and connected to a reference voltage terminal.