Wiring line and manufacture process thereof, and semiconductor device and manufacturing process thereof

• US 6,545,359 B1
• Filed: 12/16/1999
• Issued: 04/08/2003
• Est. Priority Date: 12/18/1998
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohtani, Hisashi, Yamazaki, Shunpei
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): CRUZ, LOURDES C
• Application Number:
  US09/465,083
• Time in Patent Office: 1,209 Days
• Field of Search: 257/758, 257/755, 257/757, 257/751, 257/761, 257/763
• US Class Current: 257/758
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal, and the wiring line is further protected with an anodized film. As a result, it is possible to form the wiring line having the low resistance and the high heat resistance and to form a contact with an upper line easily.

Claims

1. A wiring line comprising:

a multi-layered film comprising a first conductive layer, a second conductive layer formed on the first conductive layer and a third conductive layer formed on the second conductive layer,

wherein side surfaces of the first conductive layer, the second conductive layer and the third conductive layer and an upper surface of the third conductive layer are oxidized to form oxide film thereon, and

wherein the second conductive layer has a width different from the width of the first conductive layer and the third conductive layer.

2. A wiring line according to claim 1, wherein the oxide film is formed by anodizing.

3. A wiring line according to any one of claim 1 or 2, wherein the third conductive layer is made of a valve metal.

4. A wiring line according to any one of claim 1 or 2, wherein the second conductive layer is made of a material comprising aluminum or titanium as its main component.

5. A wiring line according to any one of claim 1 or 2, wherein the wiring line is a gate line of a thin film transistor.

34. A semiconductor device according to claim 1, wherein the second conductive layer is in contact with the first conductive layer and the third conductive layer is in contact with the second conductive layer.

6. A semiconductor device comprising:

a first wiring line including a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer and a third conductive layer on the second conductive layer;

an insulating film covering the first wiring line;

a second wiring line formed over the insulating film and electrically connected with the first wiring line; and

a contact hole extending through the insulating film and the third conductive layer,

wherein an upper surface of the second conductive layer is exposed at a bottom portion of the contact hole, and

wherein the second wiring line is connected with the upper surface of second conductive layer through the contact hole.

10. A semiconductor device according to any one of claims 6, 7, 8 and 9, wherein the second conductive layer is made of a material comprising aluminum or titanium as its main component.

11. A semiconductor device according to any one of claims 6, 7, 8 and 9, wherein the third conductive layer is made of a material containing a valve metal as its main component.

12. A semiconductor device according to any one of claims 6, 7, 8 and 9, wherein the first wiring line is a gate line of a thin film transistor.

13. A semiconductor device according to any one of claims 6, 7, 8 and 9, wherein the semiconductor device is an active matrix type electroluminescence display device.

35. A semiconductor device according to claim 6, wherein the second conductive layer is in contact with the first conductive layer and the third conductive layer is in contact with the second conductive layer.

7. A semiconductor device comprising:

a first wiring line including a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer and a third conductive layer on the second conductive layer;

an oxide film of the first, second and third conductive layers covering side surfaces and an upper surface of the first wiring line;

an insulating film covering the oxide film;

a second wiring line formed over the insulating film and electrically connected with the first wiring line; and

a contact hole extending through the insulating film, the third conductive layer and the oxide film,

wherein an upper surface of the second conductive layer is exposed at a bottom portion of the contact hole, and

wherein the second wiring line is connected with the upper surface of second conductive layer through the contact hole.

8. A semiconductor device according to claim 7, wherein the oxide film of the second conductive layer is formed by anodizing.

36. A semiconductor device according to claim 7, wherein the second conductive layer is in contact with the first conductive layer and the third conductive layer is in contact with the second conductive layer.

9. A semiconductor device comprising:

a first wiring line including a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer and a third conductive layer on the second conductive layer;

an insulating film formed over the first wiring line;

a second wiring line formed over the insulating film and electrically connected with the first wiring line; and

a contact hole extending through the insulating film and the third conductive layer,

wherein an upper surface of the second conductive layer is exposed at a bottom portion of the contact hole,

wherein the second wiring line is connected with the upper surface of second conductive layer through the contact hole,

wherein an oxide film is formed on side surfaces of the second conductive layer, and

wherein the second embodiment layer has a width different from those of the first conductive layer and the third conductive layer.

37. A semiconductor device according to claim 9, wherein the second conductive layer is in contact with the first conductive layer and the third conductive layer is in contact with the second conductive layer.

14. A semiconductor device comprising:

a p-channel thin film transistor formed over a substrate, the p-channel thin film transistor comprising;

a first semiconductor layer having a first channel region, a first source region, and a first drain region;

a first gate line formed over the first semiconductive layer with a first gate insulating film interposed therebetween, and

an n-channel thin film transistor formed over the substrate, the n-channel thin film transistor comprising;

a second semiconductor layer having a second channel region, a second source region, a second drain region, and at least one impurity region between the second channel region and the second source region;

a second gate line formed over the second semiconductor layer with a second gate insulating film interposed therebetween;

wherein the impurity region partly overlaps the second gate line with the second gate insulating film interposed therebetween, and

wherein each of the first and second gate lines includes a multi-layered film comprising a first conductive layer in contact with each of the first and second gate insulating films, a second conductive layer on the first conductive layer and a third conductive layer on the third conductive layer, and

wherein the impurity region has a lower impurity concentration than that of the second source region.

15. A semiconductor device according to claim 14, wherein the third conductive layer is a film containing a valve metal as its main component.

16. A semiconductor device according to any one of claim 14 or 15, wherein the semiconductor device is an active matrix type display device.

17. A semiconductor device according to any one of claim 14 or 15, wherein the semiconductor device is an active matrix type electroluminescence display device.

18. An electronic appliance comprising the semiconductor device according to any one of claim 14 or 15, wherein the electronic appliance is selected from the group consisting of a video camera, a digital camera, a projector, a goggle type display, a car navigation system, a personal computer and a portable information terminal.

19. A semiconductor device comprising:

a semiconductor film formed over a substrate; and

a gate electrode formed over the semiconductor film, the gate electrode having a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer,

wherein a width of the second conductive layer is smaller than those of the first and third conductive layers.

20. A wiring line according to claim 19, wherein the third conductive layer is made of a valve metal.

21. A wiring line according to claim 19, wherein the second conductive layer is made of a material comprising aluminum or titanium as its main component.

22. A semiconductor device according to claim 19, wherein the semiconductor device is an active matrix type electroluminescence display device.

23. A semiconductor device according to claim 19, wherein the semiconductor device is an active matrix type display device.

38. A semiconductor device according to claim 19, wherein the second conductive layer is in contact with the first conductive layer and the third conductive layer is in contact with the second conductive layer.

24. A semiconductor device comprising:

a semiconductor film formed over a substrate;

a gate electrode formed over the semiconductor film, the gate electrode having a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer;

an insulating film formed over the gate electrode; and

a contact hole formed through the insulating film and the third conductive layer;

a lead-out electrode formed over the insulating film,

wherein the lead-out electrode is in contact with an upper surface of the second conductive layer at a bottom portion of the contact hole.

25. A wiring line according to claim 24, wherein the third conductive layer is made of a valve metal.

26. A wiring line according to claim 24, wherein the second conductive layer is made of a material comprising aluminum or titanium as its main component.

27. A semiconductor device according to claim 24, wherein the semiconductor device is an active matrix type electroluminescence display device.

28. A semiconductor device according to claim 24, wherein the semiconductor device is an active matrix type display device.

39. A semiconductor device according to claim 24, wherein the second conductive layer is in contact with the first conductive layer and the third conductive layer is in contact with the second conductive layer.

29. A semiconductor device comprising:

a semiconductor film formed over a substrate;

a gate electrode formed over the semiconductor film, the gate electrode having a multi-layered film comprising a first conductive layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer;

an insulating film formed over the gate electrode; and

a contact hole formed through the insulating film and the third conductive layer;

a lead-out electrode formed over the insulating film,

wherein the lead-out electrode is in contact with an upper surface of the second conductive layer at a bottom portion of the contact hole, and

wherein a width of the second conductive layer is smaller than those of the first and third conductive layers.

30. A wiring line according to claim 29, wherein the third conductive layer is made of a valve metal.

31. A wiring line according to claim 29, wherein the second conductive layer is made of a material comprising aluminum or titanium as its main component.

32. A semiconductor device according to claim 29, wherein the semiconductor device is an active matrix type electroluminescence display device.

33. A semiconductor device according to claim 29, wherein the semiconductor device is an active matrix type display device.

40. A semiconductor device according to claim 29, wherein the second conductive layer is in contact with the first conductive layer and the third conductive layer is in contact with the second conductive layer.