Low leakage sleep mode for dynamic circuits

• US 6,545,512 B2
• Filed: 08/16/2001
• Issued: 04/08/2003
• Est. Priority Date: 08/16/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nowka, Kevin John
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US09/931,303
• Publication Number:
  US 20030034830A1
• Time in Patent Office: 600 Days
• Field of Search: 327/427, 327/108, 326/95, 326/96
• US Class Current: 327/108
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

In one aspect, a method for a sleep mode in a dynamic circuit includes driving a dynamic node to an operating voltage state during a precharge interval by precharge timing circuitry coupled to the dynamic node and a voltage source responsive to a precharge signal. The dynamic node is selectively pulled to a low voltage state during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The dynamic node voltage is inverted by output circuitry coupled to the dynamic node and to an output node. The output node is isolated from ground during a sleep interval responsive to a sleep signal by sleep circuitry coupled to the output circuitry.

Claims

1. Circuitry comprising:

a dynamic node;

precharge timing circuitry coupled to the dynamic node and a voltage source for driving the node to a operating voltage state during a precharge interval responsive to a precharge signal;

input circuitry coupled to the dynamic node for selectively pulling the dynamic node to a low voltage state during an evaluation interval responsive to one or more input signals;

output circuitry coupled to the dynamic node and to an output node for inverting the dynamic node voltage; and

sleep circuitry coupled to the output circuitry for selectively isolating the output node from ground during a sleep interval responsive to a sleep signal, wherein the sleep signal is functionally distinct from the precharge signal.

2. The circuitry of claim 1, wherein the circuitry is operable to pull the dynamic node signal to ground and drive the output signal to the operating voltage state during the sleep interval.

3. The circuitry of claim 2, wherein responsive to the precharge signal going to a voltage level above that of the operating voltage during the sleep interval leakage current through the precharge timing circuitry is reduced during the sleep interval.

4. The circuitry of claim 2, wherein responsive to the sleep signal going to a voltage level below ground during the sleep interval leakage current through the output circuitry is reduced during the sleep interval.

5. The circuitry of claim 1, comprising:

evaluation timing circuitry interposed between the input circuitry and ground for controlling timing of the evaluation interval responsive to an evaluation signal.

6. The circuitry of claim 1, wherein the sleep circuitry comprises a cutoff transistor.

7. A method for a sleep mode in a dynamic circuit, the method comprising the steps of driving

a dynamic node to an operating voltage state during a precharge interval responsive to a precharge signal by precharge timing circuitry coupled to the dynamic node and a voltage source;

pulling the dynamic node selectively to a low voltage state during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals;

inverting the dynamic node voltage by output circuitry coupled to the dynamic node and to an output node; and

isolating the output node from ground selectively during a sleep interval responsive to a sleep signal by sleep circuitry coupled to the output circuitry, wherein the sleep signal is functionally distinct from the precharge signal.

8. The method of claim 7, comprising the steps of:

pulling the dynamic node signal to ground during the sleep interval; and

driving the output signal to the operating voltage state during the sleep interval.

9. The method of claim 8, comprising the step of driving the precharge signal to a voltage level above that of the operating voltage during the sleep interval, so that leakage current through the precharge timing circuitry is reduced during the sleep interval.

10. The method of claim 8, comprising the step of pulling the sleep signal to a voltage level below ground during the sleep interval, so that leakage current through the output circuitry is reduced during the sleep interval.

11. The method of claim 7, comprising the step of:

controlling timing of the evaluation interval by evaluation timing circuitry interposed between the input circuitry and ground.

12. The method of claim 7, wherein the sleep circuitry comprises a cutoff transistor.