Fuse circuit configuration

• US 6,545,526 B2
• Filed: 05/29/2001
• Issued: 04/08/2003
• Est. Priority Date: 05/26/2000
• Status: Expired due to Term

• Current Assignee: ChangXin Memory Technologies, Inc.
• Original Assignee: Infineon Technologies AG
• Inventors: Honigschmid, Heinz
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/867,257
• Publication Number:
  US 20010054948A1
• Time in Patent Office: 679 Days
• Field of Search: 327/525 365/225.7,96
• US Class Current: 327/525
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A fuse circuit configuration is described wherein a compensation capacitor counteracts a parasitic capacitor. The parasitic capacitor occurs between a connection point of a switching transistor and a fuse and ground. The compensation capacitor is connected to an evaluation circuit. In this manner, the negative effects caused by the parasitic capacitor are compensated for.

Claims

1. A fuse circuit configuration, comprising:

a first switching transistor;

a second switching transistor disposed in series with said first switching transistor and defining a series circuit with a junction point disposed between said first switching transistor and said second switching transistor;

a fuse connected to said second switching transistor;

an evaluation circuit connected to said junction point and having an output at which a status of said fuse can be tapped; and

a compensation capacitor connected between said junction point and a ground terminal and counteracts a parasitic capacitor occurring between a connection point between said second switching transistor and said fuse on a first side and ground on a second side.

2. The fuse circuit configuration according to claim 1, wherein said compensation capacitor simulates a layout of a connection between said second switching transistor and said fuse.

3. The fuse circuit configuration according to claim 1, wherein said compensation capacitor has an equivalent capacitance as the parasitic capacitor.

4. A fuse circuit configuration, comprising:

a first switching transistor;

a second switching transistor disposed in series with said first switching transistor and defining a series circuit with a junction point disposed between said first switching transistor and said second switching transistor;

a fuse connected to said second switching transistor;

an evaluation circuit connected to said junction point and having an output at which a status of said fuse can be tapped;

a ground terminal; and

a compensation capacitor connected between said junction point and said ground terminal, said compensation capacitor delivering a charging current for a parasitic capacitor occurring between a connection between said second switching transistor and said fuse on a first side and said ground terminal on a second side.