Analog-to-digital converter with enhanced differential non-linearity
First Claim
Patent Images
1. A bit-and-one-half analog to digital converter comprising:
- a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage; and
a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;
wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output; and
wherein said comparator generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−
1/4 of the comparison range.
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Abstract
A bit-and-one-half analog to digital converter comprising a multiplying analog to digital converter (MDAC) operating in cooperation with a comparator which generates a two-bit digital output signal by comparison of an output of the MDAC against a pair of thresholds, wherein the thresholds are stretched outwardly from symmetrical thresholds centered at +/−1/4 of the comparison range.
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Citations
35 Claims
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1. A bit-and-one-half analog to digital converter comprising:
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a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage; and
a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;
wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output; and
wherein said comparator generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−
1/4 of the comparison range.- View Dependent Claims (2, 3, 4, 5)
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6. A multi-stage pipelined analog to digital converter comprising:
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plural stages arranged in series relative to each other, each stage accepting an input analog voltage and generating a residual analog voltage together with a digital output; and
a correction circuit for accepting the digital, output from each of said plural stages and for generating a digital output in correspondence to an analog input voltage;
wherein each stage comprises a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage and a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;
wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator of a previous one of said plural stages and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output; and
wherein said comparator generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−
1/4 of the comparison range.- View Dependent Claims (7, 8, 9, 10)
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11. A bit-and-one-half analog to digital converter comprising:
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switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage; and
comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;
wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output; and
wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−
1/4 of the comparison range.- View Dependent Claims (12, 13, 14, 15)
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16. A multi-stage pipelined analog to digital converter comprising:
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plural stage means arranged in series relative to each other, each stage means for accepting an input analog voltage and for generating a residual analog voltage together with a digital output; and
correction circuit means for accepting the digital output from each of said plural stage means and for generating a digital output in correspondence to an analog input voltage;
wherein each stage means comprises a switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage and a comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;
wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means of a previous one of said plural stage means and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output; and
wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−
1/4 of the comparison range.- View Dependent Claims (17, 18, 19, 20)
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21. A bit-and-one-half analog to digital converter comprising:
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a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage; and
a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;
wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit and in which at least another one of the capacitors is biased with a reference voltage; and
wherein said comparator generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds. - View Dependent Claims (22, 23)
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24. A multi-stage pipelined analog to digital converter comprising:
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plural stages arranged in series relative to each other, each stage accepting an input analog voltage and generating a residual analog voltage together with a digital output; and
a correction circuit for accepting the digital output from each of said plural stages and for generating a digital output in correspondence to an analog input voltage;
wherein each stage comprises a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage and a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;
wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator of a previous one of said plural stages and in which at least another on of the capacitors is biased with a reference voltage; and
wherein said comparator generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds. - View Dependent Claims (25, 26)
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27. A bit-and-one-half analog to digital converter comprising:
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switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage; and
comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;
wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit and in which at least another one of the capacitors is biased with a reference voltage; and
wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds. - View Dependent Claims (28, 29)
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30. A multi-stage pipelined analog to digital converter comprising:
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plural stage means arranged in series relative to each other, each stage means for accepting an input analog voltage and for generating a residual analog voltage together with a digital output; and
correction circuit means for accepting the digital output from each of said plural stage means and for generating a digital output in correspondence to an analog input voltage;
wherein each stage means comprises a switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage and a comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;
wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means of a previous one of said plural stage means and in which at least another one of said capacitors is biased with a reference voltage; and
wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds. - View Dependent Claims (31, 32)
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33. A method of converting an analog signal into a digital signal, comprising the steps of:
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(a) sampling an analog input during a sampling phase;
(b) storing the analog input in a plurality of capacitors;
(c) generating an amplified analog output voltage during an amplifying phase;
(d) comparing the amplified analog output voltage with a plurality of threshold voltages;
(e) switching at least one of the plurality of capacitors into a feedback arrangement; and
(f) biasing at least another one of the plurality of capacitors with a reference voltage. - View Dependent Claims (34, 35)
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Specification