Method and apparatus for writing memory arrays using external source of high programming voltage

• US 6,545,898 B1
• Filed: 06/29/2001
• Issued: 04/08/2003
• Est. Priority Date: 03/21/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Silicon Valley Bank (SVB Financial Group)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): Tran; M.
• Application Number:
  US09/897,785
• Time in Patent Office: 648 Days
• Field of Search: 365/94,96
• US Class Current: 365/94
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A passive element memory array preferably biases selected X-lines to an externally received V_PP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to V_PP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The V_PP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip V_PP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

Claims

1. In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of biasing a selected X-line at a first voltage and a group of at least one unselected Y-lines at a second voltage different than the first voltage during a write operating mode, said method comprising the steps of:

providing a source of the first voltage external to the integrated circuit;

coupling the selected X-line through at least one switch circuit to the external source of the first voltage;

providing on the integrated circuit a voltage regulator circuit responsive to the first voltage for generating a second voltage whose magnitude is less than the first voltage; and

coupling a group of at least one unselected Y-lines through at least one switch circuit to the second voltage.

2. The method as recited in claim 1 wherein:

current flow from the voltage regulator circuit to the unselected Y-lines is sourced by an external voltage source for the voltage regulator circuit having a magnitude greater than or equal to the second voltage.

3. The method as recited in claim 2 wherein:

the external voltage source for the voltage regulator circuit is substantially equal in magnitude to the programming voltage.

4. The method as recited in claim 3 wherein:

the external voltage source for the voltage regulator circuit is identical to the external source of the programming voltage.

5. The method as recited in claim 2 wherein:

the external voltage source for the voltage regulator circuit has a magnitude less than the programming voltage but higher than the second voltage.

6. The method as recited in claim 1 wherein:

the first voltage is the highest magnitude of any voltage conveyed on the integrated circuit.

7. A method as recited in claim 1 wherein:

the memory cells comprise erasable memory cells.

8. A method as recited in claim 7 wherein:

the memory array comprises a three-dimensional memory array having at least two planes of memory cells.

9. A method as recited in claim 8 wherein:

the memory cells comprise antifuse memory cells.

10. A method as recited in claim 8 wherein:

the memory cells comprise fuse memory cells.

11. A method as recited in claim 1 wherein:

the memory cells comprise write-once memory cells.

12. A method as recited in claim 11 wherein:

the memory array comprises a three-dimensional memory array having at least two planes of memory cells.

13. A method as recited in claim 12 wherein:

the memory cells comprise antifuse memory cells.

14. A method as recited in claim 12 wherein:

the memory cells comprise fuse memory cells.

15. A method as recited in claim 1 wherein:

the memory array comprises a three-dimensional memory array having at least two planes of write-once antifuse memory cells.

16. In an integrated circuit including a three-dimensional array having at least two planes of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of biasing a selected X-line at a first voltage and a group of at least one unselected Y-lines at a second voltage different than the first voltage during a write operating mode, said method comprising the steps of:

providing a voltage generator to generate a first voltage internal to the integrated circuit;

coupling the selected X-line through at least one switch circuit to the first voltage;

providing on the integrated circuit a voltage regulator circuit responsive to the first voltage for generating a second voltage whose magnitude is less than the first voltage; and

coupling a group of at least one unselected Y-lines through at least one switch circuit to the second voltage.

17. A method as recited in claim 16 wherein:

the memory cells comprise erasable memory cells.

18. A method as recited in claim 17 wherein:

the memory cells comprise antifuse memory cells.

19. A method as recited in claim 17 wherein:

the memory cells comprise fuse memory cells.

20. A method as recited in claim 16 wherein:

the memory cells comprise write-once memory cells.

21. A method as recited in claim 20 wherein:

the memory cells comprise antifuse memory cells.

22. A method as recited in claim 20 wherein:

the memory cells comprise fuse memory cells.

23. In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of biasing a selected X-line at a programming voltage and a group of at least one unselected Y-lines at a bias voltage less than the programming voltage during a write operating mode, said method comprising the steps of:

providing a programming voltage node within the integrated circuit configured to operably receive an external source of the programming voltage;

coupling the selected X-line through at least one switch circuit to the programming voltage node to thereby bias the selected X-line at substantially the programming voltage;

providing on the integrated circuit a voltage regulator circuit for generating on an unselected Y-line (UYL) bias node a second voltage whose magnitude is less than the programming voltage, wherein output current sourced by the voltage regulator circuit is provided by an external voltage source whose magnitude is higher than the second voltage; and

coupling the group of at least one unselected Y-lines through at least one respective switch circuit to the UYL bias node.

24. The method as recited in claim 23 wherein:

the external voltage source for the voltage regulator circuit is substantially equal in magnitude to the programming voltage.

25. The method as recited in claim 23 wherein:

the external voltage source for the voltage regulator circuit has a magnitude less than the programming voltage.

26. The method as recited in claim 23 wherein:

the programming voltage is the highest magnitude of any voltage conveyed on the integrated circuit.

27. The method as recited in claim 23 further comprising:

providing an unselected X-line (UXL) bias node within the integrated circuit configured to operably receive an external source of an unselected X-line (UXL) bias voltage; and

coupling a group of at least one unselected X-lines through at least one respective switch circuit to the UXL bias node.

28. A method as recited in claim 23 wherein:

the memory array comprises a three-dimensional memory array having at least two planes of write-once antifuse memory cells.

29. An integrated circuit comprising:

an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines;

a programming voltage node within the integrated circuit for operably receiving a programming voltage from an external source;

an X-line decoder circuit including a plurality of X-line switch circuits for coupling a respective X-line, when selected during a write mode of operation, to the programming voltage node;

a voltage regulator circuit having an input node for receiving an input voltage, for generating on an unselected Y-line (UYL) bias node a UYL bias voltage lower in magnitude than the programming voltage; and

a Y-line decoder circuit including a plurality of Y-line switch circuits for coupling a group of Y-lines, when unselected during the write mode of operation, to the UYL bias node.

30. The circuit as recited in claim 29 wherein:

the input voltage for the voltage regulator circuit is greater in magnitude than the UYL bias voltage but no greater than the programming voltage.

31. The circuit as recited in claim 29 wherein:

the voltage regulator circuit is configured to regulate the UYL bias voltage relative to the programming voltage.

32. The circuit as recited in claim 31 wherein:

the regulated UYL bias voltage differs from the programming voltage by a first offset value.

33. The circuit as recited in claim 32 wherein:

the first offset value falls within the range from 0.5 to 2.0 volts.

34. The circuit as recited in claim 29 wherein the X-line decoder circuit comprises:

a plurality of X-line switch circuits for coupling a respective X-line, when selected during a write mode of operation, to an associated selected X-line (SXL) bias node; and

additional switch circuits for coupling the associated SXL bias node to the programming voltage node.

35. The circuit as recited in claim 29 wherein:

the programming voltage is the highest magnitude of any voltage conveyed on the integrated circuit.

36. A circuit as recited in claim 29 wherein:

the memory array comprises a three-dimensional passive element memory array having at least two planes of write-once antifuse memory cells.

37. The circuit as recited in claim 29 wherein the voltage regulator circuit comprises:

a series device having an input terminal coupled to receive the input voltage, having an output terminal coupled to the UYL bias node, and having a control terminal; and

a feedback circuit responsive to the UYL bias voltage and responsive to a reference voltage, for generating an output signal coupled to the control terminal.

38. The circuit as recited in claim 37 wherein the feedback circuit comprises:

a reference voltage generator for generating the reference voltage; and

an amplifier circuit having a first input coupled to receive the reference voltage, having a second input coupled to receive the UYL bias voltage, and having an output coupled to the control terminal of the series device.

39. The circuit as recited in claim 37 wherein:

a voltage differential across the series device falls within the range from 0.3 to 1.0 volts.

40. The circuit as recited in claim 38 wherein:

both the reference voltage generator and the amplifier circuit are powered by the programming voltage.

41. An integrated circuit comprising:

an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines;

at least one voltage input terminal for receiving a source of operating voltage for normal read-mode operation;

at least one high voltage input terminal for receiving a source of a first high voltage; and

programming circuits configured to provide a programming current through at least one selected memory cell, wherein the programming current is provided by the source of the first high voltage by way of the at least one high voltage input terminal.

42. A circuit as recited in claim 41 further comprising:

a voltage regulator circuit responsive to the programming voltage for receiving on an input node thereof an input voltage no higher than the programming voltage and for generating on an unselected Y-line (UYL) bias node an unselected Y-line bias voltage lower in magnitude than the programming voltage.

43. In an integrated circuit including at least one memory array of passive element memory cells arranged in at least two memory planes, each memory cell of a given memory plane within a given array respectively coupled to a respective one of a plurality of X-lines associated with the given memory plane and given array, and further coupled to a corresponding one of a plurality of Y-lines associated with the given memory plane and given array, a method of programming memory cells comprising the steps of:

providing a programming voltage node within the integrated circuit configured to operably receive an external source of a programming voltage;

for each memory plane within each array having at least one memory cell to be programmed;

coupling at least some of the X-lines associated therewith to a write mode unselected X-line (UXL) bias node conveying a UXL bias voltage, and coupling at least some of the Y-lines associated therewith to a write mode unselected Y-line (UYL) bias node conveying a UYL bias voltage, both bias voltages chosen so that a particular voltage lower than a programming voltage is impressed across the memory cells coupled respectfully therebetween;

then

for each memory cell to be programmed within the memory plane and array, coupling its associated X-line to the programming voltage node while coupling its associated Y-line to a write-mode selected Y-line (SYL) voltage, both voltages chosen so that the programming voltage is impressed across the memory cell, for a time sufficient to program the memory cell.

44. A method as recited in claim 43 further comprising:

when no memory cells remain to be programmed within the array, then biasing X-lines associated with the memory plane within the array to an inactive X-line (IXL) voltage and biasing Y-lines associated with the memory plane within the array to an inactive Y-line (IYL) voltage.

45. A method as recited in claim 43 wherein:

the particular voltage, when impressed across the memory cells, reverse biases the memory cells.

46. A method as recited in claim 43 wherein:

each passive element memory cell is forward biased in a direction from its associated X-line to its associated Y-line;

each X-line is associated with memory cells within an adjacent memory plane above the X-line, if such memory plane is present, and is further associated with memory cells within an adjacent memory plane below the X-line, if such memory plane is present; and

each Y-line is associated with memory cells within an adjacent memory plane above the Y-line, if such memory plane is present, and is further associated with memory cells within an adjacent memory plane below the Y-line, if such memory plane is present.

47. A method as recited in claim 43 wherein:

each passive element memory cell within at least a first memory plane is forward biased in a direction from its associated X-line to its associated Y-line;

each passive element memory cell within at least a second memory plane adjacent to the first memory plane is forward biased in a direction from its associated Y-line to its associated X-line;

each X-line is associated with memory cells within an adjacent memory plane above the X-line, if such memory plane is present, and is further associated with memory cells within an adjacent memory plane below the X-line, if such memory plane is present; and

each Y-line is associated with memory cells within an adjacent memory plane above the Y-line, if such memory plane is present, and is further associated with memory cells within an adjacent memory plane below the Y-line, if such memory plane is present.