Self-aligned resistive plugs for forming memory cell with phase change material

• US 6,545,903 B1
• Filed: 12/17/2001
• Issued: 04/08/2003
• Est. Priority Date: 12/17/2001
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wu, Zhiqiang
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/023,392
• Time in Patent Office: 477 Days
• Field of Search: 365/148, 365/163
• US Class Current: 365/148
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Memory devices are disclosed for storage and retrieval of information, wherein resistive plugs are provided above and below a phase change material to form a memory cell. The plugs may be formed by implanting regions in high resistivity material above and below a phase change material layer to lower the resistivity in the implanted regions.

Claims

1. A memory cell for storage and retrieval of information in a memory device, comprising:

volume of phase change material disposed in a semiconductor device and comprising a generally planar upper surface and a generally planar lower surface and a memory region comprising a portion of the volume of phase change material extending between an upper portion of the upper surface and a lower portion of the lower surface;

first high resistivity material at least partially overlying the volume of phase change material and comprising a first intermediate resistivity portion contacting the upper portion of the upper surface of the memory region; and

second high resistivity material at least partially underlying the volume of phase change material and comprising a second intermediate resistivity portion contacting the lower portion of the lower surface of the memory region;

wherein phase change material in the memory region and the first and second intermediate resistivity portions form an electrical path for storage and retrieval of information in the memory cell.

2. The memory cell of claim 1, further comprising:

first conductive contact structure at least partially overlying the first intermediate resistivity portion of the first high resistivity material and electrically contacting the first intermediate resistivity portion; and

second conductive contact structure at least partially underlying the second intermediate resistivity portion of the second high resistivity material and electrically contacting the second intermediate resistivity portion;

wherein an applied voltage across the first and second conductive contact structures causes a current to flow in the phase change material in the memory region and the first and second intermediate resistivity portions.

3. The memory cell of claim 2, wherein at least one of the first and second intermediate resistivity portions comprise high resistivity material implanted with at least one of boron, arsenic, and phosphorus, and wherein a resistivity associated with the at least one of the first and second intermediate resistivity portions is less than a resistivity associated with one of the first and second high resistivity materials.

4. The memory cell of claim 3, wherein the memory region and the first and second intermediate resistivity portions are aligned along a vertical axis.

5. The memory cell of claim 2, wherein the volume of phase change material comprises an electrically switchable chalcogenide alloy formed of antimony, tellurium, and germanium, wherein the first and second high resistivity materials comprise one of undoped polysilicon and amorphous silicon, and wherein at least one of the first and second intermediate resistivity portions comprise high resistivity material implanted with at least one of boron, arsenic, and phosphorus.

6. The memory cell of claim 2, wherein the volume of phase change material is located in a generally horizontal plane and wherein the first and second intermediate resistivity portions are symmetrical with respect to one another about the plane.

7. The memory cell of claim 1, wherein at least one of the first and second intermediate resistivity portions comprises high resistivity material implanted with at least one of boron, arsenic, and phosphorus, and wherein a resistivity associated with the at least one of the first and second intermediate resistivity portions is less than a resistivity associated with one of the first and second high resistivity materials.

8. The memory cell of claim 1, wherein the memory region and the first and second intermediate resistivity portions are aligned along a vertical axis.

9. The memory cell of claim 1, wherein the volume of phase change material comprises an electrically switchable chalcogenide alloy formed of antimony, tellurium, and germanium, wherein the first and second high resistivity materials comprise one of undoped polysilicon and amorphous silicon, and wherein at least one of the first and second intermediate resistivity portions comprises high resistivity material implanted with at least one of boron, arsenic, and phosphorus.

10. The memory cell of claim 1, wherein the volume of phase change material is located in a generally horizontal plane and wherein the first and second intermediate resistivity portions are symmetrical with respect to one another about the plane.

11. A memory device for storage and retrieval of information, comprising:

an array of electrically programmable and erasable memory cells individually operative for storage and retrieval at least one data bit; and

means for reading and writing the array of memory cells;

wherein at least one of the memory cells comprises;

volume of phase change material disposed in a semiconductor device and comprising a generally planar upper surface and a generally planar lower surface and a memory region comprising a portion of the volume of phase change material extending between an upper portion of the upper surface and a lower portion of the lower surface;

first high resistivity material at least partially overlying the volume of phase change material and comprising a first intermediate resistivity portion contacting the upper portion of the upper surface of the memory region; and

second high resistivity material at least partially underlying the volume of phase change material and comprising a second intermediate resistivity portion contacting the lower portion of the lower surface of the memory region.

12. The memory device of claim 11, wherein phase change material in the memory region and the first and second intermediate resistivity portions form an electrical path for storage and retrieval of information in the at least one of the memory cells.

13. The memory device of claim 11, wherein at least one of the first and second intermediate resistivity portions comprises high resistivity material implanted with at least one of boron, arsenic, and phosphorus, and wherein a resistivity associated with the at least one of the first and second intermediate resistivity portions is less than a resistivity associated with one of the first and second high resistivity materials.

14. The memory device of claim 11, wherein the memory region and the first and second intermediate resistivity portions are aligned along a vertical axis.

15. The memory device of claim 11, wherein the volume of phase change material comprises an electrically switchable chalcogenide alloy formed of antimony, tellurium, and germanium, wherein the first and second high resistivity materials comprise one of undoped polysilicon and amorphous silicon, and wherein at least one of the first and second intermediate resistivity portions comprises high resistivity material implanted with at least one of boron, arsenic, and phosphorus.

16. A method of fabricating a memory cell in a semiconductor memory device, comprising:

providing a semiconductor substrate;

depositing a first conductive contact layer over the substrate;

depositing a first high resistivity layer over the first conductive contact layer;

depositing a volume of phase change material over the first high resistivity layer, the volume of phase change material comprising a memory region comprising a portion of the volume of phase change material extending between generally planar upper and lower surfaces of the volume of phase change material;

depositing a second high resistivity layer over the volume of phase change material;

depositing a second conductive contact layer over the second high resistivity layer;

forming a first intermediate resistivity portion in the first high resistivity layer substantially beneath the memory region; and

forming a second intermediate resistivity portion in the second high resistivity layer substantially above the memory region.

17. The method of claim 16, wherein depositing the first and second high resistivity layers comprises depositing one of undoped polysilicon and amorphous silicon.

18. The method of claim 16, wherein depositing the volume of phase change material comprises depositing a chalcogenide alloy formed of antimony, tellurium, and germanium over the first high resistivity layer.

19. The method of claim 16, wherein forming the first and second intermediate resistivity portions comprises reducing first and second resistivities associated with the first and second intermediate resistivity portions of the first and second high resistivity layers, respectively.

20. The method of claim 19, wherein reducing the first resistivity of the first intermediate resistivity portion comprises implanting at least one of boron, arsenic, and phosphorus in the first intermediate resistivity portion.

21. The method of claim 19, wherein reducing the second resistivity of the second intermediate resistivity portion comprises implanting at least one of boron, arsenic, and phosphorus in the second intermediate resistivity portion.

22. The method of claim 19, wherein reducing the first and second resistivities comprises implanting at least one of boron, arsenic, and phosphorus in the first and second intermediate resistivity portions using a single implantation process.

23. The method of claim 22, wherein implanting at least one of boron, arsenic, and phosphorus in the first and second intermediate resistivity portions comprises implanting the first and second intermediate resistivity portions using a single mask, and wherein the first and second intermediate resistivity portions are vertically aligned with respect to one another.