Antifuse programming current limiter
First Claim
Patent Images
1. An antifuse bank, comprising:
- a signal source for providing a high voltage level for programming the antifuse bank;
at least one antifuse having a dielectric interposed between two electrodes;
at least one selector to select the at least one antifuse corresponding to an address;
a current sensor having a sense terminal coupled to one electrode of the at least one antifuse and further having an enable terminal, the current sensor providing an active enable signal in response to sensing a current at the sense terminal exceeding a current threshold; and
a current limiter having a first connection coupled to the signal source, a second connection coupled to the enable terminal, and a third connection coupled to the at least one selector, the current limiter allowing current to be inhibited from flowing through the at least one antifuse in response to an active enable signal.
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Abstract
Methods for enhancing the programming of antifuses are discussed. The methods include accessing an antifuse in an antifuse bank by providing an address, raising a signal source to a high voltage level for programming the antifuse, sensing current flowing through the antifuse, and inhibiting current from flowing through the antifuse without having to delay by a programmed time period when the current is sensed by the act of sensing. The act of inhibiting continues to inhibit current from flowing until another address is provided. The methods also include accessing antifuses in multiple banks and programming them simultaneously.
39 Citations
40 Claims
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1. An antifuse bank, comprising:
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a signal source for providing a high voltage level for programming the antifuse bank;
at least one antifuse having a dielectric interposed between two electrodes;
at least one selector to select the at least one antifuse corresponding to an address;
a current sensor having a sense terminal coupled to one electrode of the at least one antifuse and further having an enable terminal, the current sensor providing an active enable signal in response to sensing a current at the sense terminal exceeding a current threshold; and
a current limiter having a first connection coupled to the signal source, a second connection coupled to the enable terminal, and a third connection coupled to the at least one selector, the current limiter allowing current to be inhibited from flowing through the at least one antifuse in response to an active enable signal. - View Dependent Claims (2, 3, 4, 5)
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6. A computer system, comprising:
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a processor;
a memory system that comprises a plurality of memory modules, one of the plurality of the memory modules comprises a plurality of memory devices;
a plurality of command links coupled to the plurality of memory devices to communicate at least one command signal;
a plurality of data links coupled to the plurality of memory devices to communicate data;
a memory controller;
at least one user interface device, wherein the at least one user interface device includes a monitor;
at least one output device, wherein the at least one output device includes a printer;
at least one bulk storage device, wherein at least one memory device of the plurality of memory devices includes an antifuse bank comprising;
a signal source having a high voltage level for programming the antifuse bank;
at least one antifuse having a dielectric interposed between two electrodes;
at least one selector to select the at least one antifuse corresponding to an address;
a current sensor having a sense terminal coupled to one electrode of the at least one antifuse and further having an enable terminal, the current sensor providing an active enable signal in response to sensing a current at the sense terminal exceeding a current threshold; and
a current limiter having a first terminal coupled to the signal source, a second terminal coupled to the enable terminal, and a third terminal coupled to the at least one selector, in response to an active enable signal, the current limiter inhibiting current from flowing through the at least one antifuse until the at least one access circuit receives another address, without having to delay by a delay circuit for a programmed time period.
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7. A method for programming an antifuse bank, comprising:
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accessing the antifuse bank by providing a row address and a column address;
raising a signal source to a high voltage level for programming the antifuse bank;
programming an antifuse by coupling the antifuse to the signal source; and
inhibiting current from flowing through the antifuse without delaying by a programmed time period and sensing current flowing through the antifuse before the act of inhibiting is executed. - View Dependent Claims (8, 9, 10)
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11. An antifuse bank, comprising:
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a signal source having a high voltage level for programming the antifuse bank;
at least one antifuse having a dielectric interposed between two electrodes;
at least one current sensor having one terminal coupled to the signal source and another terminal coupled to the at least one antifuse;
at least one selector to select the at least one antifuse corresponding to an address;
at least one switch having a first electrode coupled to the at least one antifuse, a second electrode coupled to the at least one selector, and a third electrode; and
an inhibitor coupled to the third electrode of the at least one switch, the inhibitor inhibiting current from flowing through the at least one antifuse by opening the at least one switch without having to delay by a programmed time period. - View Dependent Claims (12, 13, 14, 15)
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16. A method for programming an antifuse bank, comprising:
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accessing an antifuse by providing an address;
raising a signal source to a high voltage level for programming the antifuse;
sensing current flowing through the antifuse; and
inhibiting current from flowing through the antifuse without delaying by a delaying circuitry when the current is sensed by the act of sensing, wherein the act of inhibiting continues to inhibit current from flowing until reading of the programmed state of the antifuse is desired, or accessing another fuse in the bank is desired. - View Dependent Claims (17, 18, 19, 20)
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21. A method for limiting current through an antifuse, comprising:
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closing a switch that couples the antifuse to a selector;
selecting the antifuse for programming by providing an address to the selector;
detecting a voltage from sensing current flowing through the antifuse;
generating an enabled signal when the act of detecting detects the voltage; and
inhibiting current from flowing through the antifuse when the enabled signal is generated by opening the switch until the address is changed or reading the fuse is desired. - View Dependent Claims (22, 23, 24, 25)
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26. A circuit for enhancing programming of an antifuse bank which includes multiple antifuses, each antifuse having a dielectric between two electrodes, the circuit comprising:
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a signal source for programming an antifuse;
at least one resistor having a lead coupled to the voltage source, and another lead coupled to one of the two electrodes of the antifuse to define a node;
at least one switching transistor having a gate, a source, and a drain coupled to the other of the two electrodes of the antifuse; and
a latch having a complementary output coupled to the gate of the at least one switching transistor and providing a control signal out of the complementary output to control the at least one switching transistor, the latch transitioning the control signal to reverse-bias the at least one switching transistor when sufficient current flows across the at least one resistor, the latch transitioning the control signal to forward-bias the at least one switching transistor when inhibiting current is no longer desired. - View Dependent Claims (27, 28, 29, 30)
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31. A method for enhancing programming of an antifuse bank which includes a set of antifuses, each antifuse having a dielectric between two electrodes, the method comprising:
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providing a signal source for programming an antifuse;
sensing current by at least one resistor having a lead coupled to the voltage source, and another lead coupled to one of the two electrodes of the antifuse to define a node;
switching by at least one switching transistor having a gate, a source, and a drain, wherein the drain of the at least one switching transistor is coupled to the other of the two electrodes of the antifuse; and
latching by a latch having a complementary output coupled to the gate of the at least one switching transistor and providing a control signal out of the complementary output to control the at least one switching transistor, the latch transitioning the control signal to reverse-bias the at least one switching transistor when current flows across the at least one resistor, the latch transitioning the control signal to forward-bias the at least one switching transistor when inhibiting current is no longer desired. - View Dependent Claims (32, 33, 34, 35)
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36. A number of antifuse banks, each antifuse bank comprising:
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a signal source for programming the number of antifuse banks;
a plurality of antifuses in each antifuse bank, the plurality of antifuses coupled to the signal source, the plurality of antifuses adapted to be accessed by a plurality of row addresses and one column address;
a current sensor coupled to each antifuse bank for generating an enable signal in response to sensing a current exceeding a current threshold; and
a current limiter coupled to the plurality of antifuses for inhibiting current from flowing through the plurality of antifuses in response to the enable signal without having to delay by a programmed time period. - View Dependent Claims (37, 38, 39, 40)
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Specification