Write circuit of a memory device

• US 6,545,937 B2
• Filed: 04/22/2002
• Issued: 04/08/2003
• Est. Priority Date: 09/16/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pawlowski, J. Thomas
• Primary Examiner(s): Lam, David
• Application Number:
  US10/127,368
• Publication Number:
  US 20020191477A1
• Time in Patent Office: 351 Days
• Field of Search: 365/230.06, 365/230.08, 365/230.02, 365/189.01, 365/189.02, 365/189.05, 365/189.12, 365/189.11
• US Class Current: 365/189.15
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

A data input circuit including a first input register, a second input register, and a write driver connected to the second input register. The first and second input registers are preferably series-connected. In the preferred embodiment, a multiplexer selectively connects one of the first and second input registers to the write driver. The input circuit may be embodied in a memory device and in memory systems.

Claims

1. A write circuit for a memory device, the write circuit comprising:

a first data input register for latching data on a data bus of the memory device;

a second data input register connected to the first data input register;

a selective connector connected to the first data input register and the second data input register; and

a write driver connected to the selective connector, wherein the selective connector is for selectively coupling one of the first and second data input registers to the write driver.

2. The write circuit of claim 1, wherein the first data input register includes a data input terminal for connection to the data bus of the memory device.

3. The write circuit of claim 2, wherein the first data input register includes an enable terminal for connection to an input enable register of the memory device.

4. The write circuit of claim 3, wherein the first data input register includes a data output terminal connected to:

a data input terminal of the second data input register; and

a data input terminal of the selective connector.

5. The write circuit of claim 4, wherein the data output terminal of the first data input register is for connection to a read circuit of the memory device.

6. The write of claim 5, wherein the data output terminal of the first data input register is for connection to a selective connector of the read circuit of the memory device.

7. The write circuit of claim 1, wherein the second data input register includes a data input terminal connected to a data output terminal of the first data input register.

8. The write circuit of claim 7, wherein the second data input register includes an enable terminal for connection to an input enable register of the memory device.

9. The write circuit of claim 8, wherein the second data input register includes a data output terminal connected to a data input terminal of the selective connector.

10. The write circuit of claim 1, wherein the selective connector includes:

a first data input terminal connected to a data output terminal of the first data input register;

a second data input terminal connected to a data output terminal of the second input register; and

a data output terminal connected to a data input terminal of the write driver.

11. The write circuit of claim 10, wherein the data output terminal of the selective connector is for connection to a read circuit of the memory device.

12. The write circuit of claim 11, wherein the data output terminal of the selective connector is for connection to a selective connector of the read circuit of the memory device.

13. The write circuit of claim 12, wherein the selective connector includes a control terminal for connection to an output terminal of a second selective connector.

14. The write circuit of claim 1, wherein the selective connector includes a multiplexer.

15. The write of claim 14, wherein the selective connector includes a plurality of selective connectors.

16. The write circuit of claim 1, wherein the write driver includes a data input terminal connected to an output terminal of the selective connector.

17. The write circuit of claim 16, wherein the write driver includes an enable terminal for connection to a logic gate of the memory device.

18. The write circuit of claim 17, wherein the logic gate is an AND gate.

19. The write circuit of claim 18, wherein the write driver includes data output terminal for connection to a memory array of the memory device.

20. The write circuit of claim 1, wherein the write driver includes a plurality of write drivers.

21. A memory device, comprising:

a memory array;

an address circuit coupled to the memory array;

a read circuit coupled to the memory array;

a data bus coupled to the read circuit;

a write circuit coupled to the memory array, wherein the write circuit includes;

a first data input register for latching data on the data bus;

a second data input register connected to the first data input register;

a selective connector connected to the first data input register and the second data input register; and

a write driver connected to the selective connector, wherein the selective connector is for selectively connecting one of the first and second data input registers to the write driver; and

a control circuit coupled to the address circuit, the read circuit, and the write circuit.

22. A memory system, comprising:

control logic; and

a memory device in communication with the control logic, wherein the memory device includes;

a memory array;

an address circuit coupled to the memory array;

a read circuit coupled to the memory array;

a data bus coupled to the read circuit;

a write circuit coupled to the memory array, wherein the write circuit includes;

a first data input register for latching data on the data bus;

a second data input register connected to the first data input register;

a selective connector connected to the first data input register and the second data input register; and

a write driver connected to the selective connector, wherein the selective connector is for selectively connecting one of the first and second data input registers to the write driver; and

a control circuit coupled to the address circuit, the read circuit, and the write circuit.

23. The memory system of claim 22, wherein the memory system includes a plurality of memory devices in communication with the control logic.