Methods and apparatus for transmitting data in a public network

• US 6,546,024 B1
• Filed: 06/30/1998
• Issued: 04/08/2003
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Henniger, Mick, Aiyagari, Sanjay K., Coffeng, Gregory M., Meggitt, Warren, Sharper, Craig
• Primary Examiner(s): Nguyen, Chau
• Assistant Examiner(s): HYUN, SOON D
• Application Number:
  US09/107,840
• Time in Patent Office: 1,743 Days
• Field of Search: 370/465, 370/466, 370/470, 370/476, 370/545, 370/542, 370/543, 375/260, 375/222
• US Class Current: 370/470
• CPC Class Codes: H04J 3/04 Distributors combined with modulators or demodulators pulse distributors in general H03K5/15; pulse counters H03K21/00 - H03K29/06; for telegraphy H04L5/22, H04L13/00 - H04L23/00, H04L25/45; for telephony H04Q11/04
• CPC Class Codes: H04J 3/07 using pulse stuffing for systems with different or fluctuating information rates or bit rates
• CPC Class Codes: H04J 3/1641 Hierarchical systems
• CPC Class Codes: H04Q 11/0421 Circuit arrangements therefor
• CPC Class Codes: H04Q 2213/13034 A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/13039 Asymmetrical two-way transmission, e.g. ADSL, HDSL
• CPC Class Codes: H04Q 2213/13174 Data transmission, file transfer
• CPC Class Codes: H04Q 2213/13214 Clock signals
• CPC Class Codes: H04Q 2213/13216 Code signals, frame structure
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13297 Coupling different rates in TDM systems, data rate adaptation
• CPC Class Codes: H04Q 2213/13322 Integrated circuits
• CPC Class Codes: H04Q 2213/1336 Synchronisation

Abstract

Methods and apparatus for transmitting and receiving data using framing circuitry designed to generate data frames of a first duration at a first data rate. According to the invention, data frames are generated and decomposed at lower data rates than the rate for which the framing circuitry was originally designed, i.e., the first data rate. The framing circuitry is programmed to organize a data stream into a sequence of data frames of the first duration or to decompose such data frames into a data stream. According to the invention, such a sequence of data frames corresponds to a selected one of a plurality of equivalent data rates. Each of the equivalent data rates are lower than the first data rate.

Claims

1. An apparatus for transmitting a data stream, comprising:

framing circuitry designed to generate a first sequence of data frames each having a first duration, the first sequence of data frames corresponding to a first data rate, the framing circuitry being programmed to receive and organize the data stream into a second sequence of data frames each having the first duration, the second sequence of data frames corresponding to a selected one of a plurality of equivalent data rates and a selected one of a plurality of framed data rates, each of the equivalent and framed data rates being lower than the first data rate;

modulation circuitry for modulating the second sequence of data frames and transmitting the modulated second sequence of data frames at the selected framed data rate;

first clock circuitry operable to provide any of a first plurality of clock signals to the framing circuitry, each of the first plurality of clock signals corresponding to one of the plurality of equivalent data rates; and

second clock circuitry operable to provide any of a second plurality of clock signals to the modulation circuitry, each of the second plurality of clock signals corresponding to one of the plurality of framed data rates.

2. The apparatus of claim 1 wherein the framing circuitry includes a plurality of registers each of which corresponds to a data frame attribute, a first one of the registers corresponding to a first data frame attribute having an attribute value stored therein corresponding to the selected equivalent data rate.

3. The apparatus of claim 2 wherein the first data frame attribute corresponds to a number of data bits in a data frame payload block.

4. The apparatus of claim 1 wherein the framing circuitry is designed to generate the first sequence of data frames according to a high data rate digital subscriber line (HDSL) standard format and the first duration is 6 ms.

5. The apparatus of claim 1 wherein the modulation circuitry modulates the second sequence of data frames according to a 2B1Q encoding scheme.

6. The apparatus of claim 1 wherein the modulation circuitry comprises a bit pump.

7. The apparatus of claim 1 wherein the first clock circuitry comprises a plurality of oscillators each of which corresponds to one of the first plurality of clock signals.

8. The apparatus of claim 1 wherein the first clock circuitry comprises an oscillator and multiplier circuitry which is programmable to generate each of the first plurality of clock signals.

9. The apparatus of claim 1 wherein the second clock circuitry comprises a plurality of oscillators each of which corresponds to one of the second plurality of clock signals.

10. An apparatus for receiving a modulated sequence of data frames transmitted at a selected one of a plurality of framed data rates, comprising:

demodulation circuitry for demodulating the modulated sequence of data frames thereby generating a demodulated sequence of data frames each having a first duration, the demodulated sequence of data frames corresponding to the selected framed data rate;

framing circuitry designed to decompose a first sequence of data frames each having the first duration into a first data stream corresponding to a first data rate, the framing circuitry being programmed to receive and decompose the demodulated sequence of data frames into a second data stream corresponding to a selected one of a plurality of equivalent data rates, each of the equivalent and framed data rates being lower than the first data rate;

first clock circuitry operable to provide any of a first plurality of clock signals to the framing circuitry, each of the first plurality of clock signals corresponding to one of the plurality of equivalent data rates; and

second clock circuitry operable to provide any of a second plurality of clock signals to the demodulation circuitry, each of the second plurality of clock signals corresponding to one of the plurality of framed data rates.

11. The apparatus of claim 10 wherein the framing circuitry includes a plurality of registers each of which corresponds to a data frame attribute, a first one of the registers corresponding to a first data frame attribute having an attribute value stored therein corresponding to the selected equivalent data rate.

12. The apparatus of claim 11 wherein the first data frame attribute corresponds to a number of data bits in a data frame payload block.

13. The apparatus of claim 10 wherein the first sequence of data frames conform to a high data rate digital subscriber line (HDSL) standard format and the first duration is 6 ms.

14. The apparatus of claim 10 wherein the demodulation circuitry demodulates the modulated sequence of data frames according to a 2B1Q decoding scheme.

15. The apparatus of claim 10 wherein the demodulation circuitry comprises a bit pump.

16. The apparatus of claim 10 wherein the first clock circuitry comprises a plurality of oscillators each of which corresponds to one of the first plurality of clock signals.

17. The apparatus of claim 10 wherein the first clock circuitry comprises an oscillator and multiplier circuitry operable to generate each of the first plurality of clock signals.

18. The apparatus of claim 10 wherein the second clock circuitry comprises a plurality of oscillators each of which corresponds to one of the second plurality of clock signals.

19. A method for transmitting a data stream, comprising:

receiving the data stream with framing circuitry designed to generate a first sequence of data frames each having a first duration, the first sequence of data frames corresponding to a first data rate;

organizing the data stream with the framing circuitry and associated first clock circuitry into a second sequence of data frames each having the first duration, the second sequence of data frames corresponding to a selected one of a plurality of equivalent data rates and a selected one of a plurality of framed data rates, each of the equivalent and framed data rates being lower than the first data rate;

modulating the second sequence of data frames using second clock circuitry; and

transmitting the modulated second sequence of data frames at the selected framed data rate.

20. The method of claim 19 wherein the framing circuitry includes a plurality of registers each of which corresponds to a data frame attribute, a first one of the registers corresponding to a first data frame attribute, the method further comprising programming the first register with an attribute value corresponding to the selected equivalent data rate.

21. The method of claim 20 wherein the first data frame attribute corresponds to a number of data bits in a data frame payload block.

22. The method of claim 19 wherein the framing circuitry is designed to generate the first sequence of data frames according to a high data rate digital subscriber line (HDSL) standard format and the first duration is 6 ms.

23. The method of claim 19 wherein modulating the second sequence of data frames comprises encoding the second sequence of data frames using a 2B1Q encoding scheme.

24. The method of claim 19 wherein the framing circuitry is clocked by clock circuitry comprising a plurality of oscillators each of which corresponds to one of a plurality of clock signals, the method further comprising selecting one of the plurality of oscillators thereby providing a selected one of the plurality of clock signals to the framing circuitry, the selected clock signal corresponding to the selected equivalent data rate.

25. The method of claim 19 wherein the framing circuitry is clocked by clock circuitry comprising an oscillator and multiplier circuitry which is programmable to generate each of a plurality of clock signals, the method further comprising programming the multiplier circuitry thereby providing a selected one of the plurality of clock signals to the framing circuitry, the selected clock signal corresponding to the selected equivalent data rate.

26. The method of claim 19 wherein modulating the second sequence of data frames is achieved with modulation circuitry which is clocked by clock circuitry comprising a plurality of oscillators each of which corresponds to one of a plurality of clock signals, the method further comprising selecting one of the plurality of oscillators thereby providing a selected one of the plurality of clock signals to the modulation circuitry, the selected clock signal corresponding to the selected framed data rate.

27. A method for receiving a modulated sequence of data frames transmitted at a selected one of a plurality of framed data rates, comprising:

receiving the modulated sequence of data frames;

demodulating the modulated sequence of data frames using first clock circuitry thereby generating a demodulated sequence of data frames each having a first duration, the demodulated sequence of data frames corresponding to the selected framed data rate; and

decomposing the demodulated sequence of data frames into a decomposed data stream corresponding to a selected one of a plurality of equivalent data rates, the decomposing being achieved with second clock circuitry, and framing circuitry designed to decompose a first sequence of data frames each having the first duration into a first data stream corresponding to a first data rate, each of the equivalent and framed data rates being lower than the first data rate.

28. The method of claim 27 wherein the framing circuitry includes a plurality of registers each of which corresponds to a data frame attribute, a first one of the registers corresponding to a first data frame attribute, the method further comprising programming the first register with an attribute value corresponding to the selected equivalent data rate.

29. The method of claim 28 wherein the first data frame attribute corresponds to a number of data bits in a data frame payload block.

30. The method of claim 27 wherein the framing circuitry is designed to generate the first sequence of data frames according to a high data rate digital subscriber line (HDSL) standard format and the first duration is 6 ms.

31. The method of claim 27 wherein demodulating the modulated sequence of data frames comprises decoding the modulated sequence of data frames using a 2B1Q decoding scheme.

32. The method of claim 27 wherein the framing circuitry is clocked by clock circuitry comprising a plurality of oscillators each of which corresponds to one of a plurality of clock signals, the method further comprising selecting one of the plurality of oscillators thereby providing a selected one of the plurality of clock signals to the framing circuitry, the selected clock signal corresponding to the selected equivalent data rate.

33. The method of claim 27 wherein the framing circuitry is clocked by clock circuitry comprising an oscillator and multiplier circuitry which is programmable to generate each of a plurality of clock signals, the method further comprising programming the multiplier circuitry thereby providing a selected one of the plurality of clock signals to the framing circuitry, the selected clock signal corresponding to the selected equivalent data rate.

34. The method of claim 27 wherein demodulating the modulated sequence of data frames is achieved with demodulation circuitry which is clocked by clock circuitry comprising a plurality of oscillators each of which corresponds to one of a plurality of clock signals, the method further comprising selecting one of the plurality of oscillators thereby providing a selected one of the plurality of clock signals to the demodulation circuitry, the selected clock signal corresponding to the selected framed data rate.

35. An apparatus for organizing a data stream into a sequence of data frames comprising framing circuitry designed to generate a first sequence of data frames each having a first duration, the first sequence of data frames corresponding to a first data rate, the framing circuitry being programmed to receive and organize the data stream using clock circuitry into a second sequence of data frames each having the first duration, the second sequence of data frames corresponding to a selected one of a plurality of equivalent data rates, each of the equivalent data rates being lower than the first data rate,

wherein the framing circuitry is designed to generate the first sequence of data frames according to a high data rate digital subscriber line (HDSL) standard format and the first duration is 6ms.

36. An apparatus for decomposing a sequence of data frames into a data stream comprising framing circuitry designed to decompose a first sequence of data frames each having a first duration into a first data stream corresponding to a first data rate, the framing circuitry being programmed to receive a second sequence of data frames each having the first duration and decompose the second sequence of data frames using clock circuitry into a second data stream corresponding to a selected one of a plurality of equivalent data rates, each of the equivalent data rates being lower than the first data rate,

wherein the framing circuitry is designed to decompose the first sequence of data frames corresponding to a high data rate digital subscriber line (HDSL) standard format and the first duration is 6 ms.

37. A method for organizing a first data stream into a first sequence of data frames comprising:

receiving the first data stream with framing circuitry designed to generate a second sequence of data frames each having a first duration, the second sequence of data frames corresponding to a first data rate; and

organizing the first data stream with the framing circuitry and associated clock circuitry into the first sequence of data frames each having the first duration, the first sequence of data frames corresponding to a selected one of a plurality of equivalent data rates, each of the equivalent data rates being lower than the first data rate,

wherein the framing circuitry is designed to generate the second sequence of data frames corresponding to a high data rate digital subscriber line (HDSL) standard format and the first duration is 6 ms.

38. A method for decomposing a first sequence of data frames into a first data stream comprising:

receiving the first sequence of data frames with framing circuitry designed to decompose a second sequence of data frames each having a first duration into a second data stream, the second data stream corresponding to a first data rate; and

decomposing the first sequence of data frames each having the first duration using clock circuitry into the first data stream corresponding to a selected one of a plurality of equivalent data rates, each of the equivalent data rates being lower than the first data rate,

wherein the framing circuitry is designed to decompose the second sequence of data frames corresponding to a high data rate digital subscriber line (HDSL) standard format and the first duration is 6 ms.