Point-of-sale system

• US 6,546,441 B1
• Filed: 04/20/1999
• Issued: 04/08/2003
• Est. Priority Date: 01/26/1993
• Status: Expired due to Term

• Current Assignee: Logic Controls Incorporated
• Original Assignee: Logic Controls Incorporated
• Inventors: Lum, Jackson
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): NGUYEN, TANH Q
• Application Number:
  US09/295,619
• Time in Patent Office: 1,449 Days
• Field of Search: 705/16, 705/21, 705/25, 705/43, 705/44, 710/2-3, 710/8-12, 710/15-19, 710/29, 710/36-40, 710/51, 710/52, 710/59, 710/62-65, 710/72-74, 710/101-105, 710/126, 710/129, 710/268, 709/102-103, 709/208, 709/245, 709/220-226, 709/252-253
• US Class Current: 710/72
• CPC Class Codes: G06Q 20/20 Point-of-sale [POS] network systems
• CPC Class Codes: G06Q 20/202 Interconnection or interaction of plural electronic cash registers [ECR] or to host computer, e.g. network details, transfer of information from host to ECR or from ECR to ECR
• CPC Class Codes: G07G 1/12 electronically operated digital data processing aspects G06Q20/00

Abstract

A point-of-sale system is disclosed which is freely configurable with a plurality of peripheral input devices. The system includes a general purpose computer having a communications port for receiving and/or transmitting data. An electronic interface is coupled to the communications port and readily connectable to the plurality of peripheral input devices for communicating data between the plurality of input devices and the computer. The plurality of peripheral input devices can be selectively connected and disconnected from the electronic interface, the electronic interface maintaining a continuous dialogue with the computer during the connection and disconnection of the input devices.

Claims

1. An apparatus for serially connecting a plurality of peripheral input devices to a general purpose computer, said apparatus including an interface comprising:

an interface input and an interface output, said interface output being operatively connected to the computer and said interface input being operatively connected to a first peripheral input device;

a peripheral device port operatively connecting a second peripheral input device to said interface;

a microprocessor operatively connected to said interface input, said microprocessor monitoring data communications between the computer and said first peripheral input device, said microprocessor generating a signal in accordance with traffic conditions on the serial connection between the computer and the peripheral input devices, said signal having a first value indicative of the occurrence of said data communications between said computer and said first peripheral input device, said signal having a second value indicative of the computer being available for data communication with said second peripheral input device when there is no traffic on the serial connection between the computer and the peripheral input devices; and

,

a multiplexer operatively connected between said interface input and said interface output, and selectively providing an electrical connection between said interface input, said interface output and said peripheral device port, said multiplexer having a control input operatively connected to said microprocessor and being responsive to said signal from the microprocessor, said multiplexer performing one of the following functions;

(i) when said signal is at said first value, directing data received from said interface input directly to said interface output without requiring the data to pass through the microprocessor; and

,

(ii) when said signal is at said second value, directing data received from said peripheral device port to said interface output.

2. An apparatus according to claim 1, further including a second interface comprising:

an interface input and an interface output, said interface output of the second interface being operatively coupled to the interface input of said interface, and said interface input of the second interface being operatively connected to said first peripheral input device;

a peripheral device port operatively connecting a third peripheral input device to said second interface,

a microprocessor operatively connected to said interface input of the second interface, said microprocessor of the second interface monitoring data communications between the computer and said first peripheral input device, said microprocessor of the second interface generating a signal in accordance with traffic conditions on the serial connection between the computer and the peripheral input devices, said signal from the microprocessor of the second interface having a first value indicative of the occurrence of said data communications between said computer and said first peripheral input device, said signal from the microprocessor of the second interface having a second value indicative of when there is no traffic on the serial connection between the computer and the peripheral input devices the computer being available for data communication with said third peripheral input device; and

,

a multiplexer operatively connected between said interface input of the second interface and said interface output of the second interface, and selectively providing an electrical connection between said interface input of the second interface, said interface output of the second interface and said peripheral device port of the second interface, said multiplexer of the second interface having a control input operatively connected to said microprocessor of the second interface and being responsive to said signal from the microprocessor of the second interface, said multiplexer of the second interface performing one of the following functions;

(i) when said signal from the microprocessor of the second interface is at said first value, directing data received from said interface input of the second interface directly to said interface output of the second interface without requiring the data to pass through the microprocessor of the second interface; and

,

(ii) when said signal from the microprocessor of the second interface is at said second value, directing data received from said peripheral device port of the second interface to said interface output of the second interface.

3. An apparatus according to claim 1, wherein said multiplexer maintains electrical connection between said interface input and said interface output until said signal is at said second value, wherein said multiplexer directs data communication between said second peripheral input device and the computer.

4. An apparatus according to claim 3, wherein said multiplexer re-establishes electrical connection between said interface input and said interface output after said second peripheral input device has completed said data communication with the computer.

5. An apparatus according to claim 2, wherein said multiplexer in said second interface maintains electrical connection between said interface input of the second interface and said interface output of the second interface until said signal from the microprocessor of the second interface is at said second value, wherein said multiplexer in said second interface directs data communication between said third peripheral input device and the computer.

6. An apparatus according to claim 5, wherein said multiplexer in said second interface re-establishes electrical connection between said interface input of the second interface and said interface output of the second interface after said third peripheral input device has completed said data communication with the computer.

7. An apparatus according to claim 1, wherein said interface further comprises memory, operatively connected to said microprocessor, said microprocessor storing data received from said second peripheral input device in said memory when the computer is communicating with said first peripheral input device, said microprocessor transmitting said data stored in said memory when the computer is available for communicating with said second peripheral input device, thereby avoiding bus contention.

8. An interface according to claim 2, wherein said second interface further comprises memory, operatively connected to said microprocessor of the second interface, said microprocessor of the second interface storing data received from said third peripheral input device in said memory of the second interface when the computer is communicating with said first peripheral input device, said microprocessor of the second interface transmitting said data stored in said memory of the second interface when the computer is available for communicating with said third peripheral input device, thereby avoiding bus contention.

9. An apparatus according to claim 2, further comprising:

a conversion circuit for converting data received from said second peripheral input device in a first predetermined format to a second predetermined format, said second format being compatible with said general purpose computer.

10. An apparatus according to claim 9, further comprising:

a second conversion circuit for converting data received from said third peripheral input device in a third predetermined format to said second predetermined format for communicating with said general purpose computer.

11. An apparatus according to claim 9, wherein said second predetermined format is RS232 format.

12. An apparatus according to claim 10, wherein said second predetermined format is RS232 format.

13. An apparatus according to claim 2, further comprising a plurality of said interfaces operatively connected in a daisy chain configuration to said interface input, wherein said first peripheral input device is operatively connected to an interface input of a last interface of said daisy chain.

14. An apparatus according to claim 7, wherein said memory is located in said microprocessor.

15. An apparatus according to claim 8, wherein said memory is located in said microprocessor of the second interface.

16. An apparatus according to claim 1, wherein said plurality of peripheral input devices are selected from the group consisting of an optical scanner, a point-of-sale keyboard, a magnetic stripe reader, an electronic scale and a computer keyboard.

17. An apparatus according to claim 2, wherein at least one of said first peripheral input device, said second peripheral input device, and said third peripheral input device is selected from the group consisting of an optical scanner, a point-of-sale keyboard, a magnetic stripe reader, an electronic scale and a computer keyboard.

18. An apparatus according to claim 1, wherein said plurality of peripheral input devices are operatively connected to a keyboard input port of the general purpose computer.

19. An apparatus according to claim 1, wherein said plurality of peripheral input devices are operatively connected to an RS232 port of the general purpose computer.

40. An apparatus according to claim 1, wherein when said signal is at said second value, said data received from said peripheral device port is directed to said interface output through the microprocessor.

20. An apparatus for serially connecting a plurality of peripheral input devices to a communications port of a general purpose computer, said apparatus including an interface comprising:

an interface input and an interface output, said interface output being operatively connected to the computer and said interface input being operatively connected to a first peripheral input device;

a peripheral device port operatively connecting a second peripheral input device to said interface;

a microprocessor operatively connected to said interface input, said microprocessor monitoring data communications between the computer and said first peripheral input device, said microprocessor generating a signal in accordance to with traffic conditions on the serial connection between the computer and the peripheral input devices, said signal having a first value indicative of the occurrence of said data communications between said computer and said first peripheral input device, said signal having a second value indicative of when there is no traffic on the serial connection between the computer and the peripheral input devices the computer being available for data communication with said second peripheral input device; and

,

a multiplexer operatively connected between said interface input and said interface output, and selectively providing an electrical connection between said interface input, said interface output and said peripheral device port, said multiplexer having a control input operatively connected to said microprocessor and being responsive to said signal from the microprocessor, said multiplexer performing one of the following functions;

(i) when said signal is at said first value, directing data received from said interface input directly to said interface output without requiring the data to pass through the microprocessor; and

,

(ii) when said signal is at said second value, directing data received from said peripheral device port to said interface output.

21. An apparatus according to claim 20, further including a second interface comprising:

an interface input and an interface output, said interface output of the second interface being operatively coupled to the interface input of said interface, and said interface input of the second interface being operatively connected to said first peripheral input device;

a peripheral device port operatively connecting a third peripheral input device to said second interface,

a microprocessor operatively connected to said interface input of the second interface, said microprocessor of the second interface monitoring data communications between the computer and said first peripheral input device, said microprocessor of the second interface generating a signal in accordance with traffic conditions on the serial connection between the computer and the peripheral input devices, said signal from the second interface having a first value indicative of the occurrence of said data communications between said computer and said first peripheral input device, said signal from the second interface having a second value indicative of the computer being available for data communication with said third peripheral input device when there is no traffic on the serial connection between the computer and the peripheral input devices; and

,

a multiplexer operatively connected between said interface input of the second interface and said interface output of the second interface, and selectively providing an electrical connection between said interface input of the second interface, said interface output of the second interface and said peripheral device port of the second interface, said multiplexer of the second interface having a control input operatively connected to said microprocessor of the second interface and being responsive to said signal from the microprocessor of the second interface, said multiplexer of the second interface performing one of the following functions;

(i) when said signal from the microprocessor of the second interface is at said first value, directing data received from said interface input of the second interface directly to said interface output of the second interface without requiring the data to pass through the microprocessor of the second interface; and

,

(ii) when said signal from the microprocessor of the second interface is at said second value, directing data received from said peripheral device port of the second interface to said interface output of the second interface.

22. An apparatus according to claim 20, wherein said multiplexer maintains electrical connection between said interface input and said interface output until said signal is at said second value, wherein said multiplexer directs data communication between said second peripheral input device and the computer.

23. An apparatus according to claim 22, wherein said multiplexer re-establishes electrical connection between said interface input and said interface output after said second peripheral input device has completed said data communication with the computer.

24. An apparatus according to claim 21, wherein said multiplexer in said second interface maintains electrical connection between said interface input of the second interface and said interface output of the second interface until said signal from the microprocessor of the second interface is at said second value, wherein said multiplexer in said second interface directs data communication between said third peripheral input device and the computer.

25. An apparatus according to claim 24, wherein said multiplexer in said second interface re-establishes electrical connection between said interface input of the second interface and said interface output of the second interface after said third peripheral input device has completed said data communication with the computer.

26. An apparatus according to claim 20, further comprising a computer executable software program for controlling said interface and said plurality of peripheral input devices, wherein the computer executes said software program and assigns a unique identification code to each of said plurality of peripheral devices, and

wherein said interface further comprises memory which stores said unique identification code, said memory being operatively connected to said microprocessor which utilizes said unique identification code to compare with an address received with data from the computer, to determine if it is the intended recipient of data transmitted by the computer, and causes the corresponding peripheral device to execute the transmitted data if the unique identification code matches said address, and

wherein said microprocessor stores data received from said second peripheral input device in said memory when the computer is communicating with said first peripheral input device, and wherein said microprocessor transmits said data stored in said memory when the computer is available for communicating with said second peripheral input device, thereby avoiding bus contention.

27. An interface according to claim 21, further comprising a computer executable software program for controlling said interface, said second interface and said plurality of peripheral input devices, wherein the computer executes said software program and assigns a unique identification code to each of said plurality of peripheral devices, and

wherein said interface further comprises memory which stores said unique identification code, said memory being operatively connected to said microprocessor in the interface which utilizes said unique identification code to compare with an address received with data from the computer, to determine if it is the intended recipient of data transmitted by the computer, and causes the corresponding peripheral device to execute the transmitted data if the unique identification code matches said address, and

wherein said second interface further comprises memory which stores said unique identification code, said memory of the second interface being operatively connected to said microprocessor in said second interface which utilizes said unique identification code to compare with an address received with data from the computer, to determine if it is the intended recipient of data transmitted by the computer, and causes the corresponding third peripheral device to execute the transmitted data if the unique identification code matches said address, and

wherein said memory of the second interface is operatively connected to said microprocessor of the second interface, said microprocessor of the second interface storing data received from said third peripheral input device in said memory of the second interface when the computer is communicating with said first peripheral input device, said microprocessor of the second interface transmitting said data stored in said memory of the second interface when the computer is available for communicating with said third peripheral input device, thereby avoiding bus contention.

28. An apparatus according to claim 21, further comprising:

a conversion circuit for converting data received from said second peripheral input device in a first predetermined format to a second predetermined format, said second format being compatible with said general purpose computer.

29. An apparatus according to claim 28, further comprising:

a second conversion circuit for converting data received from said third peripheral input device in a third predetermined format to said second predetermined format for communicating with said general purpose computer.

30. An apparatus according to claim 28, wherein said second predetermined format is RS232 format.

31. An apparatus according to claim 29, wherein said second predetermined format is RS232 format.

32. An apparatus according to claim 21, further comprising a computer executable software program for controlling said interface, said second interface and said plurality of peripheral input devices, wherein the computer executes said software program and assigns a unique identification code to each of said plurality of peripheral devices, and

wherein said interface further comprises memory which stores said unique identification code, said memory being operatively connected to said microprocessor which utilizes said unique identification code to compare with an address received with data from the computer, to determine if it is the intended recipient of data transmitted by the computer, and causes the corresponding peripheral device to execute the transmitted data if the unique identification code matches said address, and

wherein said second interface further comprises memory which stores said unique identification code, said memory of the second interface being operatively connected to said microprocessor in said second interface which utilizes said unique identification code to compare with an address received with data from the computer, to determine if it is the intended recipient of data transmitted by the computer, and causes the corresponding third peripheral device to execute the transmitted data if the unique identification code matches said address, and

wherein said apparatus further comprises a plurality of said interfaces operatively connected in a daisy chain configuration to said interface input, wherein said first peripheral input device is operatively connected to an interface input of a last interface of said daisy chain.

33. An apparatus according to claim 26, wherein said memory is located in said microprocessor.

34. An apparatus according to claim 27, wherein said memory is located in said microprocessor of the second interface.

35. An apparatus according to claim 20, wherein at least one of said first peripheral input device and said second peripheral input device is selected from the group consisting of an optical scanner, a point-of-sale keyboard, a magnetic stripe reader, an electronic scale and a computer keyboard.

36. An apparatus according to claim 21, wherein said plurality of peripheral input devices are selected from the group consisting of an optical scanner, a point-of-sale keyboard, a magnetic stripe reader, an electronic scale and a computer.

37. An apparatus according to claim 20, wherein said plurality of peripheral input devices are operatively connected to a keyboard input port of the general purpose computer.

38. An apparatus according to claim 20, wherein said plurality of peripheral input devices are operatively connected to an RS232 port of the general purpose computer.

39. An apparatus according to claim 32, wherein said computer executes a power-on initialization routine whereby said unique identification codes are assigned to at least one of said plurality of peripheral input devices.

41. An apparatus according to claim 20, wherein when said signal is at said second value, said data received from said peripheral device port is directed to said interface output through the microprocessor.