Synchronous memory device having automatic precharge

• US 6,546,446 B2
• Filed: 12/21/2001
• Issued: 04/08/2003
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US10/028,077
• Publication Number:
  US 20020091890A1
• Time in Patent Office: 473 Days
• Field of Search: 365/230.03, 365/200, 365/203, 365/205, 365/207, 365/208, 710/100, 710/305
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A synchronous integrated circuit memory device including an array of memory cells. The memory device includes a clock receiver to receive an external clock signal, and a plurality of sense amplifiers, coupled to the array of memory cells, to sense data. A first portion of the data is output from the memory device in response to a first operation code bit specifying a read operation. In addition, the memory device includes a first input receiver to sample the first operation code bit in response to a first transition of the external clock signal. Furthermore, the memory device includes a second input receiver to sample a second operation code bit in response to the first transition of the external clock signal. The second operation code bit indicates whether precharging the plurality of sense amplifiers occurs automatically after the data has been sensed. Moreover, the memory device includes a plurality of output drivers to output the portion of the data synchronously with respect to the external clock signal.

Claims

1. A synchronous;

integrated circuit device having a memory array which includes dynamic random access memory cells, wherein the integrated circuit device comprises;

a clock receiver to receive an external clock signal;

a plurality of sense amplifiers, coupled to the memory array, to sense data from the dynamic random access memory cells; and

a plurality of input receivers to sample an operation code synchronously with respect to the external clock signal, the operation code including precharge information, wherein, in response to the precharge information, the plurality of sense amplifiers is automatically precharged after the data is sensed.

2. The integrated circuit device of claim 1 wherein the operation code specifies a read operation, and wherein the integrated circuit device further includes a plurality of output drivers to output first and second portions of the data in response to the operation code specifying a read operation.

3. The integrated circuit device of claim 2 wherein:

the plurality of output drivers output the first portion of the data synchronously with respect to a rising edge transition of the external clock signal; and

the plurality of output drivers output a second portion of the data synchronously with respect to a falling edge transition of the external clock signal.

4. The integrated circuit device of claim 2 further including a delay lock loop, coupled to the plurality of output drivers, to synchronize the output of the first and second portions of the data with the external clock signal.

5. The integrated circuit device of claim 2 further including a plurality of multiplexers to provide the first and second portions of data to the plurality of output drivers, wherein each multiplexer of the plurality of multiplexers is coupled to a respective output driver of the plurality of output drivers.

6. The integrated circuit device of claim 5 wherein:

the plurality of multiplexers provide the first portion of the data to the plurality of output drivers in response to a rising transition of the external clock signal; and

the plurality of multiplexers provide the second portion of the data to the plurality of output drivers in response to a falling edge transition of the external clock signal.

7. The integrated circuit device of claim 1 wherein the plurality of input receivers further includes a first input receiver to sample a first bit of the operation code synchronously with respect to the external clock signal, wherein the precharge information is encoded in the first bit of the operation code.

8. The integrated circuit device of claim 7 wherein the plurality of input receivers further includes a second input receiver to sample a second bit of the operation code synchronously with respect to the external clock signal, wherein the second bit of the operation code specifies a read operation, wherein a portion of the data is output from the integrated circuit device in response to the second bit of the operation code specifying the read operation.

9. The integrated circuit device of claim 8 wherein the plurality of input receivers further includes a third input receiver to sample address information synchronously with respect the external clock signal.

10. The integrated circuit device of claim 1 wherein the operation code includes a plurality of bits that, in combination, encode information which specifies that the plurality of sense amplifiers sense the data from the memory array.

11. The integrated circuit device of claim 1 further including row decoder circuitry, coupled to the memory array, to identify, in response to a row address, a row of the memory array that stores the data to be sensed by the plurality of sense amplifiers.

12. The integrated circuit device of claim 1 further including column decoder circuitry, coupled to the plurality of sense amplifiers, to identify, in response to a column address, a portion of the data.

13. The integrated circuit device of claim 1 further including a clock synchronization circuit coupled to the clock receiver, wherein the clock synchronization circuit includes:

a delay line to generate an internal clock signal, wherein the internal clock signal has a delay with respect to the external clock signal; and

a comparator to compare the internal clock signal with the external clock signal, wherein the delay of the internal clock signal is adjusted based on the comparison between the internal clock signal and the external clock signal.

14. The integrated circuit device of claim 13 further including a plurality of output drivers to output first and second portions of the data in response to the operation code specifying a read operation, wherein the clock synchronization circuit is coupled to the plurality of output drivers to synchronize the output of the first and second portions of the data with the external clock signal.

15. The integrated circuit device of claim 14 wherein the plurality of input receivers samples the operation code from a plurality of external signal lines of an external bus, wherein the external bus is used to carry, in a multiplexed format, the operation code, and the first and second portions of the data.

16. A synchronous integrated circuit memory device including an array of memory cells, wherein the memory device comprises:

a clock receiver to receive an external clock signal;

a plurality of sense amplifiers, coupled to the array of memory cells, to sense data, wherein a portion of the data is output from the memory device in response to a first operation code bit specifying a read operation;

a first input receiver to sample the first operation code bit in response to a first transition of the external clock signal;

a second input receiver to sample a second operation code bit in response to the first transition of the external clock signal, wherein the second operation code bit indicates whether precharging the plurality of sense amplifiers occurs automatically after the data has been sensed; and

a plurality of output drivers to output the portion of the data synchronously with respect to the external clock signal.

17. The memory device of claim 16 wherein the second input receiver further samples an address bit synchronously with respect to a second transition of the external clock signal.

18. The memory device of claim 16 wherein the plurality of output drivers output the portion of the data onto an external bus, the external bus including a plurality of external signal lines.

19. The memory device of claim 18 wherein:

the first operation code bit is sampled from a first signal line of the plurality of external signal lines; and

the second operation code bit is sampled from a second signal line of the plurality of external signal lines.

20. The memory device of claim 19 wherein the plurality of external signal lines is used to carry, in a multiplexed format, address information and the portion of the data.

21. The memory device of claim 16 further including a delay locked loop, coupled to the clock receiver, to generate an internal clock signal using the external clock signal, wherein the plurality of output drivers output the portion of the data in response to the internal clock signal.

22. The memory device of claim 16 further including:

row decoder circuitry, coupled to the array of memory cells, to identify a row of the array of memory cells that stores the data to be sensed by the plurality of sense amplifiers; and

column decoder circuitry, coupled to the plurality of sense amplifiers, to identify the portion of the data.

23. A method of operation of a synchronous integrated circuit memory device, wherein the memory device includes an array of memory cells, wherein the method of operation of the memory device comprises:

sampling an operation code in response to a first transition of an external clock signal, wherein the operation code specifies a read operation and includes precharge information;

sensing data in a plurality of sense amplifiers, wherein the data is output in response to the operation code specifying the read operation;

automatically precharging the plurality of sense amplifiers in response to the precharge information, wherein the plurality of sense amplifiers is automatically precharged after the data is sensed; and

outputting the data synchronously with respect to the external clock signal.

24. The method of claim 23 further including sampling address information synchronously with respect to the external clock signal, wherein the address information identifies;

a location of the data within the array.

25. The method of claim 24 wherein the operation code and the address information are included in a request packet.

26. The method of claim 24 wherein the operation code and the address information are sampled from an external bus, wherein the external bus includes a plurality of signal lines to carry the address information and the operation code in a multiplexed format.

27. The method of claim 26 wherein the data is output onto the plurality of signal lines.

28. The method of claim 23 further including:

selecting a row of memory cell locations in accordance with a first address portion; and

sensing data, from the selected row of memory cell locations, in a row of sense amplifiers, wherein the plurality of sense amplifiers is included in the row of sense amplifiers.

29. The method of claim 28 further including identifying the data sensed in the plurality of sense amplifiers based on a second address portion.

30. The method of claim 23 further including generating an internal clock signal using a delay locked loop, wherein the data is output in response to the internal clock signal.

31. The method of claim 23 wherein outputting the data includes:

outputting a first portion of the data synchronously with respect to a rising edge transition of the external clock signal; and

outputting a second portion of the data synchronously with respect to a falling edge transition of the external clock signal.

32. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of sense amplifiers coupled to a memory cell array, wherein the method of controlling the memory device comprises:

providing a first operation code to the memory device, wherein the first operation code indicate that the memory device;

output data read from the memory cell array; and

precharge sense amplifiers used in reading the data from the memory cell array, wherein the sense amplifiers used in reading the data are precharge automatically after the data is read from the memory cell array; and

receiving the data from the memory device, the memory device outputting the data in response to the first operation code.

33. The method of claim 32 wherein the first operation code is included in a request packet.

34. The method of claim 32 further including providing a second operation code to the memory device, wherein the second operation code instructs the memory device to:

receive input data to be written to the memory cell array;

write the input data to the memory cell array using sense amplifiers of the plurality of sense amplifiers; and

precharge the sense amplifiers used in writing the input data to the memory cell array, wherein the sense amplifiers are precharged automatically after the input data is written to the memory cell array.

35. The method of claim 34 further including:

providing, to the memory device, a row address and a column address; and

providing a third operation code to the memory device, wherein the third operation code instructs the memory device to;

output data read from a specified location of the memory cell array, wherein the specified location is identified by the row address and the column address; and

retaining, in at least a portion of the plurality of sense amplifiers, the data read from the specified location of the memory cell array.

36. The method of claim 32 further including:

providing, to the memory device, a row address; and

providing a second operation code to the memory device, wherein the second operation code includes bits that, in combination, encode information which indicates that the memory device sense data from a specified location of the memory cell array using at least a portion of the plurality of sense amplifiers, wherein the specified location is identified by the row address.

37. The method of claim 32 further including providing address information to the memory device, wherein the address information is provided synchronously with respect to the external clock signal.

38. The method of claim 37 wherein the address information and the first operation code are issued to the memory device via an external bus.

39. A synchronous memory device having a memory array which includes dynamic memory cells, wherein the memory device comprises:

a plurality of sense amplifiers, coupled to the memory array, to sense data from the dynamic memory cells;

a plurality of input receivers to sample an operation code synchronously with respect to an external clock signal, the operation code including precharge information, wherein, in response to the precharge information, the plurality of sense amplifiers is automatically precharged after the data is sense;

a plurality of output drivers to output first and second portions of the data in response to the operation code specifying a read operation; and

a delay locked loop, coupled to the plurality of output drivers, to synchronize the output of the first and second portions of the data with the external clock signal.

40. The memory device of claim 39 wherein:

the plurality of output drivers output the first portion of the data synchronously with respect to a rising edge transition of the external clock signal; and

the plurality of output drivers output the second portion of the data synchronously with respect to a falling edge transition of the external clock signal.

41. The memory device of claim 39 further including a plurality of multiplexers, wherein each multiplexer of the plurality of multiplexers is coupled to a respective output driver of the plurality of output drivers.

42. The memory device of claim 41 wherein the plurality of multiplexers provides the first portion of the data to the plurality of output drivers in response to a rising edge transition of the external clock signal, and wherein the plurality of multiplexers provides the second portion of the data to the plurality of output drivers in response to a falling edge transition of the external clock signal.

43. The memory device of claim 39 wherein the plurality of input receivers further includes a first input receiver to sample a first bit of the operation code synchronously with respect to the external clock signal, wherein the precharge information is encoded in the first bit of the operation code.

44. The memory device of claim 43 wherein the plurality of input receivers further includes a second input receiver to sample a second bit of the operation code synchronously with respect to the external clock signal, wherein an encoding of the second bit of the operation code specifies the read operation.

45. The memory device of claim 39 wherein the delay locked loop includes:

a delay line to generate an internal clock signal, wherein the internal clock signal has a delay with respect to the external clock signal; and

a comparator to compare the internal clock signal with the external clock signal, wherein the delay of the internal clock signal is adjusted based on the comparison between the internal clock signal and the external clock signal, wherein the output of the first and second portions of the data is synchronized with the external clock signal using the internal clock signal.