Synchronous semiconductor memory device capable of reducing test cost and method of testing the same

• US 6,546,503 B2
• Filed: 07/09/2002
• Issued: 04/08/2003
• Est. Priority Date: 01/19/1999
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ooishi, Tsukasa
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US10/190,693
• Publication Number:
  US 20020194546A1
• Time in Patent Office: 273 Days
• Field of Search: 714/5-8, 714/25, 714/30, 714/48, 714/733, 714/724, 714/37, 714/718, 714/735, 714/763, 365/200, 365/201, 711/100
• US Class Current: 714/6.2
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders

Abstract

A match detection circuit detecting match of data outputted to a plurality of data terminals is provided on an input/output circuit part. In a test, the same result is written in two latches, and alternately read in response to a clock signal. From a terminal outputting data at a double data rate in general, therefore, a test result can be outputted at a lower data rate. Observation is enabled with a tester having low performance, for reducing the cost for the test.

Claims

1. A semiconductor device, comprising:

a memory array;

a BIST (built-in self test) control circuit controlling execution of a self test for said memory array, supplying an address and a command to said memory array and communicating storage data with said memory array; and

a register unit holding a result of said self test, said register unit including a program circuit storing said result of said self test in a nonvolatile manner.

2. The semiconductor device according to claim 1, wherein said memory array includes a plurality of normal memory cells, and a plurality of redundant memory cells;

and said result of said self test includes an address information corresponding to one of said plurality of normal memory cells to be substituted for one of said plurality of redundant memory cells.

3. A semiconductor device, comprising:

a memory array including a plurality of normal memory cells and a plurality of redundant memory cells; and

a program circuit storing, in a nonvolatile manner, an address information corresponding to one of said plurality of normal memory cells to be substituted for one of said plurality of redundant memory cells, said program circuit including a plurality of address register units each storing one repair address, and a, plurality of flag hold parts provided corresponding to said plurality of address register units, respectively, each storing a flag bit which shows whether or not a corresponding address register unit already stores said repair address.