Burn-in mode detect circuit for semiconductor device

• US 6,546,510 B1
• Filed: 07/13/1999
• Issued: 04/08/2003
• Est. Priority Date: 07/13/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Smith, Scott E., Mazumder, Kallol, Hii, Francis
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US09/351,384
• Time in Patent Office: 1,365 Days
• Field of Search: 714/718, 714/25, 365/201, 324/760
• US Class Current: 714/718
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A synchronous dynamic random access memory (SDRAM) is disclosed that includes an operational mode in which the functionality of the SDRAM can be tested under burn-in conditions. The SDRAM can be placed in a burn-in monitor mode in which burn-in information is provided at data outputs, in lieu of memory cell information. The burn-in monitor mode helps to ensure that the SDRAM functions are properly exercised during burn-in. The preferred embodiment includes a data buffer coupled to a data bus and a mode register. The mode register stores burn-in mode data. In a standard mode of operation, the data buffer couples the data bus to data outputs (D0-Dz). In a burn-in monitor mode of operation, the data buffer couples the burn-in mode data to the data outputs (D0-Dz).

Claims

1. A memory device, comprising:

a memory bank including a plurality of memory cells;

a data bus coupled to the memory bank;

a plurality of data outputs;

a plurality of storage registers that store burn-in mode information, and burn-in mode monitor information;

a monitor circuit coupled to at least one storage register, the monitor circuit activating a monitor enable signal when the burn-in monitor information indicates a burn-in monitor mode; and

a data buffer coupled to the data bus and the storage registers, the data buffer including

an output data path that couples the data bus to the data outputs, the output data path being disabled when the monitor enable signal is active, and

a monitor data path that couples burn-in mode information to the data outputs, the monitor data path being enabled when the monitor enable signal is active.

2. The memory device of claim 1, wherein:

the memory device includes a plurality of memory cell banks, the memory cells of a selected bank being coupled to the data bus when the selected bank is activated;

the monitor circuit places the monitor enable signal in an inactive state when a selected bank is activated; and

a data buffer includes the monitor data path being disabled when the monitor enable signal is inactive.

3. The memory device of claim 1, wherein:

the burn-in mode information stored within the plurality of storage registers includes information that indicates when the random access memory device is in a burn-in mode.

4. The memory device of claim 3, further including:

a clock buffer circuit coupled to at least one of the storage registers, the clock buffer circuit receiving an external system clock and generating an internal clock synchronous with the external system clock, the clock buffer circuit including a hysteresis control circuit that introduces hysteresis into the internal clock signal with respect to the external system clock, when enabled, the hysteresis control circuit being enabled when the burn-in mode information indicates the burn-in mode.

5. The memory device of claim 4, further including:

the burn-in mode information stored within the plurality of storage registers includes information indicating if hysteresis for the internal clock has been enabled by a command entry; and

the hysteresis control circuit of the clock buffer circuit is further enabled when the burn-in mode information indicates hysteresis is enabled.

6. The memory device of claim 1, wherein:

the burn-in mode information stored within the plurality of storage registers includes design-for-test mode information.

7. The memory device of claim 1, wherein:

the random access memory device is a synchronous random access memory; and

the burn-in mode information stored within the plurality of storage registers includes burst length information.

8. The memory device of claim 1, wherein:

the random access memory device is a synchronous random access memory; and

the burn-in mode information stored within the plurality of storage registers includes latency information.

9. The memory device of claim 1, wherein:

the random access memory device is a synchronous random access memory that includes an internal clock that is synchronous with an external system clock; and

the burn-in mode information stored within the plurality of storage registers includes information indicating if hysteresis for the internal clock is enabled.

10. A semiconductor memory device having a burn-in mode, comprising:

a data buffer that includes

a plurality of data read paths, each data read path including a multiplexer (MUX) circuit having at least a MUX first data input, a MUX second data input, a MUX data output, and a MUX control input, the MUX coupling the MUX first data input to the MUX data output when a first value is at the MUX control input, the MUX coupling the MUX second data input to the MUX data output when a second value is at the MUX control input;

a monitor enable circuit commonly coupled to the MUX control inputs of the data read paths, the monitor enable circuit generating the second value at the MUX control inputs when the semiconductor memory device is in a burn-in monitor mode; and

a data bus that provides memory bank data to the MUX first data inputs of the data read paths;

a mode register circuit that provides burn-in mode information to the MUX second data inputs of the data read paths; and

a data input/output (I/O) coupled to each MUX data output of the data buffer.

11. The semiconductor memory device of claim 10, wherein:

the MUX of each data read path includes a standard driver coupled to the MUX first data input and a bypass driver coupled to the MUX second data inputs, the standard driver being enabled and the bypass driver being disabled by the first value at the MUX control input, the standard driver being disabled and the bypass driver being enabled by the second value at the MUX control input.

12. The semiconductor memory device of claim 11, wherein:

each standard driver includes a three-state driver having one input coupled to the MUX first data input, and a second input coupled to the MUX control input.

13. The semiconductor memory device of claim 11, wherein:

each bypass driver includes a three-state driver having one input coupled to the MUX second data input, and a second input coupled to the MUX control input.

14. The semiconductor memory device of claim 11, wherein:

each bypass driver further includes a bypass default device coupled between the MUX second data input and a predetermined logic value, the bypass default device coupling the MUX second data input to the predetermined logic value when the second value is at the MUX control input.

15. The semiconductor memory device of claim 10, wherein:

the monitor enable circuit includes

a monitor enable input, and

monitor enable latching circuit that latches the logic value at the monitor enable input to provide the value at the MUX control input of the data read paths.

16. The semiconductor memory device of claim 15, wherein:

the monitor enable latch includes a set-reset flip-flop (SR-FF).

17. The semiconductor memory device of claim 16, wherein:

the semiconductor memory device generates a test clear signal to take the semiconductor memory device out of a burn-in monitor mode; and

the SR-FF has a set input coupled to monitor enable input and a reset input coupled to the test clear signal.

18. The semiconductor memory device of claim 15, wherein:

the monitor enable circuit further includes a monitor default device coupled between the monitor enable input and a predetermined logic value, the monitor default device coupling the monitor enable input to the predetermined logic value when enabled.

19. The semiconductor memory device of claim 18, wherein:

the semiconductor memory device includes a plurality memory cell banks, and generates a bank activate signal when a memory bank is accessed; and

the monitor default device is enabled by a bank activate signal.

20. The semiconductor memory device of claim 15, wherein:

the monitor enable input is coupled to the monitor enable latching circuit by a transmission gate.