Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitances

• US 6,546,541 B1
• Filed: 02/20/2001
• Issued: 04/08/2003
• Est. Priority Date: 02/20/2001
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Petranovic, Dusan, Pavisic, Ivan, Lu, Aiguo
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Thompson, A. M.
• Application Number:
  US09/789,108
• Time in Patent Office: 777 Days
• Field of Search: 716/18, 716/1-17, 716/19-21
• US Class Current: 716/104
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

A method and apparatus are provided for generating constraints for an integrated circuit logic re-synthesis algorithm. The method and apparatus receive a netlist of interconnected logic elements, which includes a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element. The method and apparatus also receive a maximum allowable input ramp time specification for the logic elements and an output ramp time specification for the net driver logic elements. A maximum interconnect capacitance constraint is then generated for each of the net driver logic elements based on the output ramp time specification for that net driver logic element and the maximum allowable input ramp time specification.

Claims

1. A method of generating constraints for an integrated circuit logic re-synthesis algorithm, the method comprising:

(a) receiving a netlist of interconnected logic elements, which includes a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element;

(b) receiving a maximum allowable input ramp time specification for the interconnected logic elements and an output ramp time specification for the net driver logic elements; and

(c) generating a maximum interconnect capacitance constraint for each of the net driver logic elements based on the output ramp time specification for the respective net driver logic element and the maximum allowable input ramp time specification.

2. The method of claim 1 and further comprising:

(d) providing the maximum interconnect capacitance constraints to a logic re-synthesis algorithm prior to routing the plurality of nets.

3. The method of claim 2 and further comprising:

(e) modifying a portion of the netlist while ensuring that each net driver in the portion drives a net that has a total capacitance of less than or equal to the maximum interconnect capacitance constraint.

4. The method of claim 1 wherein step (c) is performed after the logic elements in the netlist have been placed in a physical placement pattern and before the plurality of nets have been routed within the physical placement pattern.

5. The method of claim 1 wherein the maximum interconnect capacitance constraint generated for each of the net driver logic elements is an estimate of a total interconnect capacitance for the respective net that would result in the respective net having a degraded input ramp time, at the driven logic element, which is substantially equal to the maximum allowable input ramp time specification.

6. The method of claim 1 wherein:

step (b) comprises receiving a database of output ramp time values as a function of interconnect capacitance for each different type of the net driver logic elements; and

step (c) comprises, for each of the net driver logic elements;

(c)(1) estimating a total interconnect capacitance for the respective net that would result in the respective net having a degraded input ramp time, at the driven logic element, which is substantially equal to the maximum allowable input ramp time specification, wherein the total interconnect capacitance is estimated as a function of the output ramp time values for the respective net driver logic element and the maximum allowable input ramp time specification; and

(c)(2) setting the maximum interconnect capacitance constraint for that net driver logic element equal to the estimated total interconnect capacitance.

7. The method of claim 1 wherein step (c) comprises, for each of the net driver logic elements:

(c)(1) solving the following relation for a value of the variable, C_TOT;

$\mathrm{MAX\_RAMP}<br><br>\mathrm{\_TIME}=\frac{r_0}{{\mathrm{Ac}}_0}·<br><br>C_{\mathrm{TOT}}^2+B·<br><br>T_{\mathrm{Rdr}}<br><br>\left(C_{\mathrm{TOT}}\right)$

where C_TOT is the total interconnect capacitance of the respective net, MAX_RAMP_TIME is the maximum allowable input ramp time specification, r₀ is a unit interconnect resistance constant, c₀ is a unit interconnect capacitance constant, A and B are coefficients, and T_Rdr(C_TOT) is the output ramp time specification for the respective net driver logic element, which is a function of C_TOT; and

(c)(2) setting the maximum interconnect capacitance constraint for that net driver logic element equal to the value of C_TOT.

8. A computer-readable medium comprising instructions readable by a computer-aided design tool for optimizing a functional block within a netlist of an integrated circuit, which when executed, cause the tool to perform steps comprising:

(a) inputting the netlist, wherein the netlist comprises interconnected logic elements, including a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element;

(b) inputting a maximum allowable input ramp time specification for the interconnected logic elements and an output ramp time specification for the net driver logic elements; and

(c) generating a maximum interconnect capacitance constraint for each of the net driver logic elements based on the output ramp time specification for the respective net driver logic element and the maximum allowable input ramp time specification.

9. The computer-readable medium of claim 8 wherein the instructions further cause the tool to perform steps of:

(d) providing the maximum interconnect capacitance constraints to a logic re-synthesis algorithm, prior to routing the plurality of nets.

10. The computer-readable medium of claim 9 wherein the instructions further cause the tool to perform steps of:

(e) modifying a portion of the netlist while ensuring that each net driver in the portion drives a net that has a total capacitance of less than or equal to the maximum interconnect capacitance constraint for that net driver.

11. The computer-readable medium of claim 8 wherein step (c) is performed after the logic elements in the netlist have been placed in a physical placement pattern and before the plurality of nets have been routed within the physical placement pattern.

12. The computer-readable medium of claim 8 wherein the maximum interconnect capacitance constraint generated for each of the net driver logic elements is an estimate of a total interconnect capacitance for the respective net that would result in the respective net having a degraded input ramp time, at the driven logic element, which is substantially equal to the maximum allowable input ramp time specification.

13. The computer-readable medium of claim 8 wherein:

step (b) comprises receiving output ramp time values as a function of interconnect capacitance for each net driver logic element; and

step (c) comprises, for each of the net driver logic elements;

(c)(1) estimating a total interconnect capacitance for the respective net that would result in the respective net having a degraded input ramp time, at the driven logic element, which is substantially equal to the maximum allowable input ramp time specification, wherein the total interconnect capacitance is estimated as a function of the output ramp time values for the respective net driver logic element and the maximum allowable input ramp time specification; and

(c)(2) setting the maximum interconnect capacitance constraint for that net driver logic element equal to the estimated total interconnect capacitance.

14. The computer-readable medium of claim 8 wherein step (c) comprises, for each of the net driver logic elements:

(c)(1) solving the following relation for a value of the variable, C_TOT;

$\mathrm{MAX\_RAMP}<br><br>\mathrm{\_TIME}=\frac{r_0}{{\mathrm{Ac}}_0}·<br><br>C_{\mathrm{TOT}}^2+B·<br><br>T_{\mathrm{Rdr}}<br><br>\left(C_{\mathrm{TOT}}\right)$

where C_TOT is the total interconnect capacitance of the respective net, MAX_RAMP_TIME is the maximum allowable input ramp time specification, r₀ is a unit interconnect resistance constant, c₀ is a unit interconnect capacitance constant, A and B are coefficients, and T_Rdr(C_TOT) is the output ramp time specification for the respective net driver logic element, which is a function of C_TOT; and

(c)(2) setting the maximum interconnect capacitance constraint for that net driver logic element equal to the value of C_TOT.

15. A computer-aided design tool for optimizing a functional block within a netlist of an integrated circuit, wherein the tool comprises:

(a) means for receiving the netlist, wherein the netlist comprises interconnected logic elements, including a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element;

(b) means for receiving a maximum allowable input ramp time specification for the interconnected logic elements and an output ramp time specification for the net driver logic elements; and

(c) means for generating a maximum interconnect capacitance constraint for each of the net driver logic elements based on the output ramp time specification for the respective net driver logic element and the maximum allowable input ramp time specification.

16. The computer-aided design tool of claim 15 and further comprising:

(e) means for modifying a portion of the netlist while ensuring that each net driver in the portion drives a net that has a total capacitance of less than or equal to the maximum interconnect capacitance constraint for that net driver.

17. The computer-aided design tool of claim 15 wherein the means for generating generates the maximum interconnect capacitance constraints for the net driver logic elements with placement data representing placement of the logic elements in a physical placement pattern and without routing data representing physical routes of the plurality of nets within the physical placement pattern.

18. The computer-aided design tool of claim 15 wherein the maximum interconnect capacitance constraint generated for each of the net driver logic elements is an estimate of a total interconnect capacitance for the respective net that would result in the respective net having a degraded input ramp time, at the driven logic element, which is substantially equal to the maximum allowable input ramp time specification.

19. The computer-aided design tool of claim 15 wherein:

the means for receiving an output ramp time specification comprises means for receiving output ramp time values as a function of interconnect capacitance for each net driver logic element; and

the means for generating comprises, for each of the net driver logic elements;

(c)(1) means for estimating a total interconnect capacitance for the respective net that would result in the respective net having a degraded input ramp time, at the driven logic element, which is substantially equal to the maximum allowable input ramp time specification, wherein the total interconnect capacitance is estimated as a function of the output ramp time values for the respective net driver logic element and the maximum allowable input ramp time specification; and

(c)(2) means for setting the maximum interconnect capacitance constraint for that net driver logic element equal to the estimated total interconnect capacitance.

20. The computer-aided design tool of claim 15 wherein the means for generating comprises:

(c)(1) means for solving the following relation for a value of the variable, C_TOT;

$\mathrm{MAX\_RAMP}<br><br>\mathrm{\_TIME}=\frac{r_0}{{\mathrm{Ac}}_0}·<br><br>C_{\mathrm{TOT}}^2+B·<br><br>T_{\mathrm{Rdr}}<br><br>\left(C_{\mathrm{TOT}}\right)$

where C_TOT is the total interconnect capacitance of the respective net, MAX_RAMP_TIME is the maximum allowable input ramp time specification, r₀ is a unit interconnect resistance constant, c₀ is a unit interconnect capacitance constant, A and B are coefficients, and T_Rdr(C_TOT) is the output ramp time specification for the respective net driver logic element, which is a function of C_TOT; and

(c)(2) means for setting the maximum interconnect capacitance constraint for that net driver logic element equal to the value of C_TOT.