Method for enabling access to micro-sections of integrated circuits on a wafer

• US 6,548,314 B1
• Filed: 12/10/2001
• Issued: 04/15/2003
• Est. Priority Date: 12/10/2001
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Zaidi, Shoaib Hasan
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Luk, Olivia T
• Application Number:
  US10/015,212
• Time in Patent Office: 491 Days
• Field of Search: 438/14-17, 430/30, 430/312, 430/313
• US Class Current: 438/14
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: Y10S 977/854 Semiconductor sample
• CPC Class Codes: Y10S 977/888 Shaping or removal of materials, e.g. etching

Abstract

The present invention provides a method of enabling measurement access to small integrated circuit features that comprises selecting a feature of an integrated circuit on a wafer and providing access to the selected feature by removing a portion of the integrated circuit adjacent to the feature, thereby preserving the wafer.

Claims

1. A method for enabling measurement access to a feature of an integrated circuit device on a wafer, comprising:

selecting a feature of an integrated circuit device on a wafer; and

providing access to the selected feature for measurement thereof without destroying the wafer, including removing a portion of the integrated circuit device adjacent to the selected feature by etching said portion away.

2. The method of claim 1 wherein the removing step includes applying a coating to the wafer.

3. The method of claim 2 wherein the applying step includes applying a photosensitive resist coating to the wafer.

4. The method of claim 2 wherein the removing step includes placing a mask on the wafer, the mask revealing an area of the integrated circuit device including the selected feature.

5. The method of claim 4 wherein the placing step includes placing a lithographic mask on the wafer, the lithographic mask revealing an area of the integrated circuit device including the selected feature.

6. The method of claim 4 wherein the removing step includes exposing the area of the integrated circuit device including the selected feature.

7. The method of claim 6 wherein the exposing step includes removing the coating from the exposed area of the integrated circuit device.

8. The method of claim 6 wherein the exposing step includes etching the exposed area of the integrated circuit device.

9. The method of claim 8 including removing the coating from the wafer.

16. The method of claim 1 including inserting a measurement device into a space previously occupied by the removed portion of the integrated circuit device to thereby gain measurement access to the selected feature.

17. The method of claim 16 wherein the inserting step includes inserting an atomic force microscopy (AFM) tip into said space.

18. The method of claim 17 wherein the selected feature is a portion of a longitudinal trench, and inserting includes inserting the AFM tip into the trench in a direction generally parallel to a longitudinal direction of the trench.

19. The method of claim 18 wherein the selected feature is a sidewall angle of the longitudinal trench.

10. A method for enabling measurement access to a feature of an integrated circuit device on a wafer, comprising:

selecting a feature of an integrated circuit device on a wafer; and

providing access to the selected feature for measurement thereof without destroying the wafer, including removing a portion of the integrated circuit device adjacent to the selected feature, the removing step including applying a coating to the wafer and placing a mask on the wafer, the mask revealing an area of the integrated circuit device including the selected feature, wherein the placing step includes placing the mask at a skewed angle relative to the selected feature.

11. The method of claim 10 wherein the selected feature includes a portion of a longitudinal trench, including placing the mask at the skewed angle relative to a longitudinal direction of the longitudinal trench.

12. The method of claim 11 wherein the selected feature is a sidewall angle of a longitudinal trench.

13. A method for enabling measurement access to a feature of an integrated circuit device on a wafer, comprising:

selecting a feature of an integrated circuit device on a wafer; and

providing access to the selected feature for measurement thereof without destroying the wafer, including removing a portion of the integrated circuit device adjacent to the selected feature, wherein the selected feature includes a portion of a trench.

14. The method of claim 13 wherein the trench is a longitudinal trench.

15. The method of claim 13 wherein the selected feature is a sidewall angle of the trench.