Multi-layered gate for a CMOS imager

• US 6,548,352 B1
• Filed: 10/12/2000
• Issued: 04/15/2003
• Est. Priority Date: 06/15/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TOLEDO, FERNANDO L
• Application Number:
  US09/686,944
• Time in Patent Office: 915 Days
• Field of Search: 438/257, 438/267, 438/279, 438/316, 438/60, 438/75, 257/53, 257/83, 257/114, 257/187, 257/257, 257/444
• US Class Current: 438/257
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Abstract

A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Claims

1. A method of forming a multi-layered gate for use in an imaging device, comprising the steps of:

forming a photosensitive region of a first conductivity type on a substrate;

forming a first insulating layer over said substrate;

forming a first conductive layer over said first insulating layer;

forming a second insulating layer over said first conductive layer;

forming a first gate by etching unmasked portions of said second insulating layer, and said first conductive layer to expose a surface of said first insulating layer;

forming insulating sidewalls on lateral sides of said first gate;

after forming said insulating sidewalls, removing exposed portions of said first insulating layer to expose a surface of said substrate;

forming a fourth insulating over said exposed surface of said substrate;

forming a second gate on said fourth insulating layer and at least one of said insulating sidewalls of said first gate, and such that said second gate overlaps a section of said first gate and is formed on said second insulating layer of said first gate, wherein at least one of said first or said second gate comprises a semi-transparent conductive layer.

2. The method of claim 1, wherein said step of forming said second gate comprises forming an oxide layer over said fourth insulating layer, forming a second conductive layer over said oxide layer and forming said second gate from said oxide layer and said second conductive layer.

3. The method of claim 1, wherein said step of forming said first insulating layer comprises thermal oxidation.

4. The method of claim 1, wherein said step of forming said first insulating layer comprises deposition.

5. The method of claim 1, wherein said step of forming a first conductive layer comprises chemical vapor deposition.

6. The method of claim 1, wherein said step of forming a first conductive layer is a physical vapor deposition step.

7. The method of claim 1, further comprising forming a silicide layer on the first conductive layer prior to the step of forming said first gate.

8. The method of claim 7, wherein said step of forming said silicide layer comprises chemical vapor deposition.

9. The method of claim 7, wherein said step of forming said silicide layer further comprises forming a metal layer on the first conductive layer, and annealing the metal layer.

10. The method of claim 9, wherein the metal layer is a material selected from the group consisting of titanium, tungsten, molybdenum, tantalum, platinum, palladium, iridium, and cobalt.

11. The method of claim 9, wherein said step of forming said metal layer comprises chemical vapor deposition.

12. The method of claim 9, wherein said step of forming said metal layer comprises evaporation.

13. The method of claim 9, wherein said step of forming said metal layer comprises sputtering.

14. The method of claim 9, wherein said annealing step is carried out at a temperature within the range of approximately 300 to 900 degrees Celsius.

15. The method of claim 7, wherein said silicide layer is a layer selected from the group consisting of tungsten silicide, titanium silicide, molybdenum silicide, tantalum silicide, platinum silicide, palladium silicide, iridium silicide, and cobalt silicide.

16. The method of claim 1, wherein said step of forming said second insulating layer comprises deposition.

17. The method of claim 1, wherein said step of forming said first gate comprises directional etching of the first conductive layer and the second insulating layer.

18. The method of claim 17, wherein said directional etching is a reactive ion etch.

19. The method of claim 2, wherein said step of forming said second conductive layer comprises chemical vapor deposition.

20. The method of claim 2, wherein said step of forming said second gate comprises directional etching of the second conductive layer.

21. The method of claim 20, wherein said directional etching is a reactive ion etch.

22. The method of claim 20, wherein the first insulating layer is a layer of material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.

23. The method of claim 1, wherein the first conductive layer is a layer of doped polysilicon.

24. The method of claim 1, wherein the second insulating layer is a layer of material selected from the group consisting of deposited silicon oxide, silicon nitride, NO, ON, and ONO.

25. The method of claim 1, wherein the insulating sidewalls are formed of a material selected from the group consisting of silicon oxide, silicon spacers, silicon oxynitride, ON, NO, and ONO.

26. The method of claim 2, wherein the second conductive layer is a layer of material selected from the group consisting of doped polysilicon, tin oxide, and indium tin oxide.