Thin film transistor

• US 6,548,356 B2
• Filed: 12/13/2001
• Issued: 04/15/2003
• Est. Priority Date: 01/07/2000
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Migliorato, Piero, Miyasaka, Mitsutoshi, Yudasaka, Ichio, Lui, Basil
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, LONG K
• Application Number:
  US09/914,915
• Publication Number:
  US 20020158269A1
• Time in Patent Office: 488 Days
• Field of Search: 438/257, 438/258, 438/264-267, 438/48, 438/128, 438/149, 438/151, 438/157, 438/283, 438/263, 438/44, 438/594, 438/266, 438/372, 257/315, 257/321, 257/57, 257/59, 257/72, 257/69, 257/369, 257/351, 257/344, 257/347, 257/204, 257/206, 257/372, 257/365, 257/408, 257/66, 257/444, 257/448, 257/336
• US Class Current: 438/266
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Abstract

A semiconductor transistor comprising a substrate having an active layer formed thereon, a source and a drain formed in the active layer, a gate insulating layer formed on the active layer and a gate electrode formed on the insulating layer, wherein the gate electrode is split, the active layer has a doped region located between the source and the drain and aligned with the split in the gate electrode, and the gate electrode is aligned with the drain so as not to overlap the drain. The transistor may be formed using a method comprising the steps of: providing a semiconductor layer in which the source and drain are to be formed; forming a gate insulating layer on the semiconductor layer; forming a split gate electrode on the gate insulating layer; and using the split gate electrode as a mask in the doping of a portion of the semiconductor layer between the source and the drain of the final transistor.

Claims

1. A method of manufacturing a semiconductor transistor having a gate, a source, a drain, and a recombination region located in closer proximity to the drain in comparison to the source, comprising the steps of:

providing a semiconductor layer in which the source, drain and recombination region are to be formed;

forming a gate insulating layer on the semiconductor layer;

forming a gate electrode on the gate insulating layer, the gate electrode having a split positioned in closer proximity to a first edge of the gate electrode in comparison to a second edge of the gate electrode opposite to said first edge; and

using the gate electrode as a mask in the doping of a portion of the semiconductor layer to provide the recombination region at a position between the source and the drain in closer proximity to the drain in comparison to the source of the final transistor, thereby to reduce the kink effect of the final transistor.

2. A method as claimed in claim 1, wherein the step of using the gate electrode as a mask includes using the gate electrode as a mask in the doping of a further portion of the semiconductor layer to provide the drain aligned with said first edge of the gate electrode.

3. A method as claimed in claim 1, including the use of doping for formation of the source and wherein the step of using the gate electrode as a mask in doping involves relatively light doping as compared with the doping used for formation of the source.

4. A method claimed in claim 1, wherein between the steps of forming the gate insulating layer and forming the gate electrode, the method includes the steps of:

forming a mask, and

using the mask in doping of portions of the semiconductor layer which are to form the source and drain.

5. A method as claimed in claim 1, wherein the step of forming the gate electrode involves the formation of a multiple-split gate electrode.

6. A method as claimed in claim 5, wherein the step of using the gate electrode as a mask in doping includes using the gate electrode as a mask in doping of the source and drain as well as portions of the semiconductor layer between the source and the drain.

7. A method as claimed in claim 1, wherein the split in the gate electrode is provided at a distance of between 0.02 μ

m and 2 μ

m from the first edge of the gate electrode.

8. A method as claimed in claim 2, including the use of doping for formation of the source and wherein the step of using the gate electrode as a mask in doping involves relatively light doping as compared with the doping used for formation of the source.

9. A method as claimed in claim 2, wherein between the steps of forming the gate insulating layer and forming the gate electrode, the method includes the steps of:

forming a mask, and

using the mask in doping of portions of the semiconductor layer which are to form the source and drain.

10. A method as claimed in claim 2, wherein the step of forming the gate electrode involves the formation of a multiple-split gate.

11. A method as claimed in claim 3, wherein between the steps of forming the gate insulating layer and forming the gate electrode, the method includes the steps of:

forming a mask, and

using the mask in doping of portions of the semiconductor layer which are to form the source and drain.

12. A method as claimed in claim 5, wherein the multiple-splits are spaced at between 0.02 μ

m and 2 μ

m on the gate electrode.

13. A semiconductor transistor comprising a substrate having an active layer formed thereon, a source, a drain and a recombination region formed in the active layer, a gate insulating layer formed on the active layer and a gate electrode formed on the insulating layer, wherein the gate electrode is split at a position in closer proximity to a first edge of the gate electrode in comparison to a second edge of said electrode opposite to the first edge, the first edge of the gate electrode is aligned with the drain so as not to overlap the drain, and the recombination region is located between the source and the drain in closer proximity to the drain in comparison to the source and aligned with the split in the gate electrode for reducing the kink effect of the transistor.

14. A semiconductor transistor as claimed in claim 13, wherein the drain comprises two regions one nearer to the source than the other with the region nearer the source being relatively lightly doped compared with the other region.

15. A semiconductor transistor as claimed in claim 13, wherein the gate is a multiple-split gate and the active layer has a plurality of recombination regions located between the source and the drain and each is aligned with a respective split in the gate electrode.

16. A semiconductor transistor as claimed in claim 13, wherein the recombination regions in the active layer between the source and the drain are located nearer the drain than the source.

17. A semiconductor transistor as claimed in claim 13, wherein the split in the gate electrode is positioned at a distance of 0.02 μ

m to 2 μ

m from the first edge of the gate electrode.

18. A semiconductor transistor as claimed in claim 14, wherein the doped region or regions in the active layer between the source and the drain are located nearer the drain than the source.

19. A semiconductor transistor as claimed in claim 15, wherein the doped region or recombination regions in the active layer between the source and the drain are located nearer the drain than the source.

20. A semiconductor transistor as claimed in claim 17, wherein the gate electrode is a multiple-split gate electrode and the multiple-splits are spaced at a distance between 0.02 μ

m and 2 μ

m on the gate electrode.