Method of vertically integrating electric components by means of back contacting

• US 6,548,391 B1
• Filed: 03/18/2002
• Issued: 04/15/2003
• Est. Priority Date: 05/27/1999
• Status: Expired due to Term

• Current Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
• Original Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
• Inventors: Klumpp, Armin, Ramm, Peter
• Primary Examiner(s): Nguyen, Tuan H.
• Assistant Examiner(s): NGUYEN, THANH T
• Application Number:
  US09/979,826
• Time in Patent Office: 393 Days
• Field of Search: 438/455-456, 438/611-617
• US Class Current: 438/611
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

The present invention relates to a method of connecting two semiconductor components comprising the steps of providing in a first main surface of a first semiconductor substrate first component structures including first contact areas, forming in said first semiconductor substrate via holes filled with electrically conductive material and electrically insulated from said first semiconductor substrate, said via holes extending down to the second main surface of the first semiconductor substrate and being connected in an electrically conductive manner to said first contact areas via an electrically conductive connection material on the first main surface of said first semiconductor substrate, forming on the second main surface of the first semiconductor substrate first lands which are connected in an electrically conductive manner to the first contact areas via the electrically conductive material in the via holes, providing on a second semiconductor substrate second component structures including second contact areas, forming second lands which are connected in an electrically conductive manner to the second contact areas, and connecting the first and the second semiconductor substrate in such a way that the electrical as well as the mechanical connection between the two substrates is established via the first and the second lands. By repeating the above-mentioned steps an arbitrary number of times, a three-dimensional integrated circuit can be produced by the method according to the present invention.

Claims

1. A method of connecting two semiconductor components comprising the steps of

providing in a first main surface of a first semiconductor substrate first component structures including first contact areas;

forming in said first semiconductor substrate via holes filled with electrically conductive material and electrically insulated from said first semiconductor substrate, said via holes extending down to a second main surface of the first semiconductor substrate and being connected in an electrically conductive manner to said first contact areas via an electrically conductive connection material;

forming on the second main surface of the first semiconductor substrate first lands which are connected in an electrically conductive manner to the first contact areas via the electrically conductive material in the via holes;

providing a second semiconductor substrate having second component structures including second contact areas;

forming second lands which are connected in an electrically conductive manner to the second contact areas;

connecting the first and the second semiconductor substrate in such a way that an electrically conductive as well as a mechanically stable connection between the two substrates is established exclusively via the first and the second lands.

2. A method according to claim 1, wherein the contact areas are heavily doped connecting areas.

3. A method according to claim 1, wherein the contact areas are metallization planes.

4. A method according to claim 3, wherein the contact areas are metallization planes arranged on the first main surface.

5. A method according to claim 3, wherein the contact areas are metallization planes arranged below the first main surface.

6. A method according to claim 1, wherein the electrically conductive connection material is applied via an additional metallization sequence.

7. A method according to claim 1, wherein, after the formation of the via holes, the first main surface of the first semiconductor substrate is connected to an auxiliary substrate and is then thinned from the side of the first semiconductor substrate located opposite said first main surface.

8. A method according to claim 1, wherein the first and the second semiconductor substrate are first subjected to identical processing steps and are then joined in a mirror-inverted mode of arrangement.

9. A method according to claim 1, wherein the materials used for the first and the second land are chosen such that the compound of the first and second lands, which results from the connecting step, has a melting point which is higher than the melting points of the materials of the first and second land prior to the connecting step.

10. A method according to claim 9, wherein the materials for the first and the second land are chosen such that they will form a eutectic compound.

11. A method according to claim 1, wherein not all the first and second lands are connected in an electrically conductive manner to respective ones of the first and second contact areas.

12. A method according to claim 1, wherein an electrically conductive connection is established by placing the second main surface of the first semiconductor substrate onto the surface of the second semiconductor substrate in an aligned mode of arrangement, with a simultaneous increase in temperature and application of force.

13. A method of connecting a plurality of semiconductor components, wherein a method of connecting two semiconductor components is repeated iteratively, the method of connecting two semiconductor components having the following steps:

providing in a first main surface of a first semiconductor substrate first component structures including first contact areas;

forming in said first semiconductor substrate via holes filled with electrically conductive material and electrically insulated from said first semiconductor substrate, said via holes extending down to a second main surface of the first semiconductor substrate and being connected in an electrically conductive manner to said first contact areas via an electrically conductive connection material;

forming on the second main surface of the first semiconductor substrate first lands which are connected in an electrically conductive manner to the first contact areas via the electrically conductive material in the via holes;

providing a second semiconductor substrate having second component structures including second contact areas;

forming second lands which are connected in an electrically conductive manner to the second contact areas; and

connecting the first and the second semiconductor substrate in such a way that an electrically conductive as well as a mechanically stable connection between the two substrates is established exclusively via the first and the second lands; and

wherein the respective nth semiconductor component plays the part of the first semiconductor component, and the stack of (n−

1) combined semiconductor components plays the part of the second semiconductor component.