Methods of a high density flip chip memory arrays

• US 6,548,392 B2
• Filed: 09/17/1999
• Issued: 04/15/2003
• Est. Priority Date: 03/25/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Wood, Alan G., Akram, Salman
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US09/398,337
• Publication Number:
  US 20020058395A1
• Time in Patent Office: 1,306 Days
• Field of Search: 438/14, 438/15, 438/612, 438/13, 438/16, 438/18, 438/622, 438/17, 438/611, 438/613, 438/108
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/556 against alpha rays
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures

Abstract

A low alpha emissivity-induced error solder bump, flip-chip integrated circuit device. The device includes a semiconductor die having an active surface and a bond pad array disposed about the active surface of the die. The active surface of the die includes logic circuits adjacent memory cell arrays. Each of the bond pads directly overlays a logic circuit, to which they may be connected. The present invention also includes methods for designing and fabricating the invented devices and connecting them to a carrier substrate.

Claims

1. A method for decreasing alpha particle penetration of a solder-bumped integrated circuit having a memory cell array and at least one logic circuit, the method comprising:

providing a semiconductor die having an active surface thereon including a memory cell array and a logic circuit positioned adjacent said memory cell array;

placing at least one bond pad of the integrated circuit directly over said at least one logic circuit; and

forming a solder bump on said at least one bond pad.

2. The method of claim 1, wherein said at least one bond pad is formed directly on said at least one logic circuit.

3. The method of claim 1, further comprising forming a solder bump on said at least one bond pad.

4. The method of claim 1, further comprising encapsulating at least a portion of said semiconductor die with an encapsulant.

5. The method of claim 4, wherein said encapsulating comprises covering said active surface of said semiconductor die with said encapsulant.

6. The method of claim 4, wherein said encapsulating comprises covering all external surfaces of said semiconductor die, but for said solder bump, with said encapsulant.

7. A method for fabricating a flip-chip integrated circuit having a reduced incidence of alpha particle emissivity-induced soft errors, the method comprising:

providing a semiconductor die element having an active surface thereon;

fabricating at least one memory cell array and at least one logic circuit on said active surface of said semiconductor die element, with said at least one logic circuit positioned adjacent said at least one memory cell array;

fabricating at least one bond pad of the flip-chip integrated circuit on said active surface, over said at least one logic circuit and laterally offset from said at least one memory cell array; and

forming a solder bump on at least one bond pad of the flip-chip integrated circuit.

8. The method of claim 7, wherein at least one bond pad is operatively connected with said at least one logic circuit.

9. The method of claim 8, wherein said at least one bond pad directly overlies said at least one logic circuit.

10. A method for manufacturing a flip-chip integrated circuit, comprising:

providing a semiconductor die element having an active surface thereon;

fabricating at least one memory cell array and at least one associated logic circuit on said active surface of said semiconductor die element, with said at least one associated logic circuit positioned adjacent said at least one memory cell array, wherein said at least one memory cell array and said at least one associated logic circuit consume substantially all of said active surface;

fabricating at least one bond pad of the flip-chip integrated circuit directly over said at least one associated logic circuit; and

forming discrete external conductive elements over at least one bond pad of the flip-chip integrated circuit.

11. A method of manufacturing a reduced power flip-chip integrated circuit, comprising:

providing a semiconductor die element having an active surface thereon;

fabricating a memory cell array and at least one logic circuit on said active surface of said semiconductor die element with said at least one logic circuit positioned adjacent to said memory cell array; and

fabricating a plurality of bond pads, said plurality of bond pads being located over said at least one logic circuit.

12. A method of reconfiguring a connection pattern for a pre-existing memory device, the pre-existing memory device including an active memory element and an active non-memory circuit, the method comprising:

forming a plurality of bond pads on the memory device in an area array, each of said plurality of bond pads of the reconfigured memory device being laterally offset from the active memory element.

13. The method of claim 12, wherein each of said plurality of bond pads is formed over the active non-memory circuit.

14. The method of claim 12, further comprising placing discrete external connective elements on at least some of said plurality of bond pads.

15. A method of designing a memory device, comprising:

configuring at least one memory cell array;

configuring at least one logic circuit adjacent said at least one memory cell array; and

selecting a plurality of bond pad locations directly over said at least one logic circuit.

16. The method of claim 15, wherein each of said plurality of bond pad locations is laterally offset from said at least one memory cell array.

17. A method of connecting a flip-chip device to a carrier substrate, the flip-chip device including a semiconductor die, the semiconductor die including a plurality of memory elements and non-memory circuitry on an active surface, the method comprising:

disposing a plurality of conductive bumps over the active surface of the semiconductor die in a pattern, each of said plurality of conductive bumps being disposed over the non-memory circuitry;

inverting the flip-chip device over and substantially parallel to a surface of a carrier substrate including a plurality of terminals disposed thereon in a pattern matching the bump pattern; and

contacting said terminals and said conductive bumps and applying force transverse to the active surface through said plurality of conductive bumps to avoid said plurality of memory elements.