Apparatus for wafer-level burn-in and testing of integrated circuits
First Claim
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1. A system for reducing test time for integrated circuits on a wafer, the system comprising:
- means for powering up all die on the wafer;
means for stabilizing the integrated circuits; and
means for testing each die;
said means for powering, said means for stabilizing, and said means for testing being controlled by a circuit and being operable in a respective sequence.
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Abstract
In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.
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Citations
6 Claims
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1. A system for reducing test time for integrated circuits on a wafer, the system comprising:
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means for powering up all die on the wafer;
means for stabilizing the integrated circuits; and
means for testing each die;
said means for powering, said means for stabilizing, and said means for testing being controlled by a circuit and being operable in a respective sequence. - View Dependent Claims (2)
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3. A software system implemented to reduce test time for integrated circuits in a wafer, the software system comprising:
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means for confirming that all die on the wafer are powered up;
means for confirming that all die on the wafer are powered up;
means for confirming that said die on the wafer are stabilized subsequent to being powered up; and
means for indexing a wafer tester from one die to another until all said die have been tested. - View Dependent Claims (4, 5, 6)
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Specification