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Apparatus for wafer-level burn-in and testing of integrated circuits

  • US 6,548,826 B2
  • Filed: 03/22/2001
  • Issued: 04/15/2003
  • Est. Priority Date: 04/25/2000
  • Status: Expired due to Fees
First Claim
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1. A system for reducing test time for integrated circuits on a wafer, the system comprising:

  • means for powering up all die on the wafer;

    means for stabilizing the integrated circuits; and

    means for testing each die;

    said means for powering, said means for stabilizing, and said means for testing being controlled by a circuit and being operable in a respective sequence.

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