×

Vertical stacked gate flash memory device

  • US 6,548,856 B1
  • Filed: 05/31/2000
  • Issued: 04/15/2003
  • Est. Priority Date: 03/05/1998
  • Status: Expired due to Term
First Claim
Patent Images

1. A vertical transistor FET memory device comprising:

  • an array of FET cells formed in rows and columns, with the rows being orthogonally arranged with respect to the columns, with the cells in a single row having a common source region and with the cells in a column having separate source regions, a set of trenches each having trench sidewalls and a trench bottom in a semiconductor substrate, with threshold implant regions formed within the trench sidewalls, source connection regions formed in the substrate at the bottom of the trenches implanted with a first type of dopant, doped drain regions near the surface of the substrate juxtaposed with the trenches and doped source regions in the base of the device below the trenches with oppositely doped channel regions between the source regions and the drain regions, a tunnel oxide layer over the substrate including the sidewalls and covering the bottom of the trenches, a pair of thin floating gate strips of doped polysilicon formed over the tunnel oxide layer on both sides of the trenches extending from just below the tops of the trenches proximate to the tops of the trenches to the bottoms of the trenches and the thin floating gate strips being absent from the bottom of the trench aside from the bottoms of the sidewalls with the tunnel oxide located between the floating gate structures and the sidewalls of the trenches, the thin floating gate strips being in the form of upright thin floating gate strips along the sidewalls of the trenches, an interelectrode dielectric layer formed over the floating gate structures and the tunnel oxide layer, and a control gate layer of doped polysilicon over the interelectrode dielectric layer covering the interelectrode dielectric layer and filling the space in the trench between the thin floating gate strips.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×