Vertical stacked gate flash memory device

• US 6,548,856 B1
• Filed: 05/31/2000
• Issued: 04/15/2003
• Est. Priority Date: 03/05/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chrong-Jung, Liang, Mong-Song, Chen, Shui-Hung
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Weiss, Howard
• Application Number:
  US09/583,403
• Time in Patent Office: 1,049 Days
• Field of Search: 257/315, 257/321, 438/259
• US Class Current: 257/315
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.

Claims

1. A vertical transistor FET memory device comprising:

an array of FET cells formed in rows and columns, with the rows being orthogonally arranged with respect to the columns, with the cells in a single row having a common source region and with the cells in a column having separate source regions,

a set of trenches each having trench sidewalls and a trench bottom in a semiconductor substrate, with threshold implant regions formed within the trench sidewalls,

source connection regions formed in the substrate at the bottom of the trenches implanted with a first type of dopant,

doped drain regions near the surface of the substrate juxtaposed with the trenches and doped source regions in the base of the device below the trenches with oppositely doped channel regions between the source regions and the drain regions,

a tunnel oxide layer over the substrate including the sidewalls and covering the bottom of the trenches,

a pair of thin floating gate strips of doped polysilicon formed over the tunnel oxide layer on both sides of the trenches extending from just below the tops of the trenches proximate to the tops of the trenches to the bottoms of the trenches and the thin floating gate strips being absent from the bottom of the trench aside from the bottoms of the sidewalls with the tunnel oxide located between the floating gate structures and the sidewalls of the trenches,

the thin floating gate strips being in the form of upright thin floating gate strips along the sidewalls of the trenches,

an interelectrode dielectric layer formed over the floating gate structures and the tunnel oxide layer, and

a control gate layer of doped polysilicon over the interelectrode dielectric layer covering the interelectrode dielectric layer and filling the space in the trench between the thin floating gate strips.

2. A device in accordance with claim 1 with FOX regions formed between the rows.

3. A vertical transistor memory device with rows and columns of FET memory cells formed in and on a semiconductor substrate which has a surface, the device comprising:

an array of FET cells with rows and columns, with the rows being orthogonally arranged with respect to the columns, with the cells in a single row having a common source region and with the cells in a column having separate source regions,

FOX regions formed between the rows in the surface of the substrate,

a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions in the sidewalls,

source connection regions formed in the substrate at the bottom of the trenches implanted with a first type of dopant,

doped drain regions near the surface of the substrate juxtaposed with the trenches and doped source regions in the base of the device below the trenches with oppositely doped channel regions between the source regions and the drain regions,

a tunnel oxide layer over the substrate including the sidewalls and the bottom of the trenches,

a pair of thin floating gate strips of doped polysilicon formed over the tunnel oxide layer on both sides of the trenches with the tunnel oxide located between the floating gate structures and the sidewalls of the trenches, the thin floating gate layer being in the form of upright floating gate strips of the floating gate formed along the sidewalls of the trenches and just below the top of the trenches proximate to the drain regions at the tops of the trenches,

an interelectrode dielectric layer composed of ONO over the floating gate structures and over the tunnel oxide layer,

a thin control gate layer of doped polysilicon formed over the interelectrode dielectric layer and filling the space in the trench between the floating gate structures,

the control gate layer patterned into control gate electrodes having sidewalls, and

spacers adjacent to the sidewalls of the control gate electrodes formed over the drain regions.