DMOS transistor structure having improved performance

• US 6,548,860 B1
• Filed: 02/29/2000
• Issued: 04/15/2003
• Est. Priority Date: 02/29/2000
• Status: Expired due to Term

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Kang, Donghee
• Application Number:
  US09/515,335
• Time in Patent Office: 1,141 Days
• Field of Search: 257/335, 257/328, 257/329-331, 257/337-341, 257/334, 438/212, 438/330, 438/259, 438/270, 438/271, 438/589
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench DMOS transistor structure is provided that includes at least three individual trench DMOS transistor cells formed on a substrate of a first conductivity type. The plurality of individual DMOS transistor cells is dividable into peripheral transistor cells and interior transistor cells. Each of the individual transistor cells includes a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. A conductive electrode is located in the trench, which overlies the insulating layer. Interior transistor cells, but not the peripheral transistor cells, each further include a source region of the first conductivity type in the body region adjacent to the trench.

Claims

1. A trench DMOS transistor structure that includes at least three individual trench DMOS transistor cells formed on a substrate of a first conductivity type, said plurality of individual DMOS transistor cells being dividable into peripheral transistor cells and interior transistor cells, each of said individual transistor cells comprising:

body region on the substrate, said body region having a second conductivity type;

at least one trench extending through the body region and the substrate;

an insulating layer that lines the trench;

a conductive electrode in the trench overlying the insulating layer; and

wherein said interior transistor cells but not said peripheral transistor cells each further include a source region of the first conductivity type in the body region adjacent to the trench, and

further wherein the body regions of said peripheral transistor cells are more lightly doped than the body regions of said interior transistor cells.

2. The transitor of claim 1 wherein said body regions are substantially flat across the width of the transitor cells in which they are respectively located.

3. The transistor of claim 1 wherein said at least one trench extends to a depth below the depth of the body region.

4. The transistor of claim 3 further comprising a plurality of polysilicon contacts respectively connected to each of the conductive electrodes of the peripheral transistor cells.

5. The transistor of claim 1 wherein said body regions each have a bimodal distribution across the width of the transistor cells in which they are respectively located.

6. The transistor of claim 5 further comprising a plurality of polysilicon contacts respectively connected to each of the conductive electrodes of the peripheral transistor cells.

7. The transistor structure of claim 1 further comprising a drain electrode disposed on a surface of the substrate opposing the body region.

8. The transistor structure of claim 1 wherein said insulating layer is an oxide layer.

9. The transistor structure of claim 1 wherein said conductive electrode includes polysilicon.

10. The transistor of claim 1 wherein at least one of said trench DMOS transistor cells has a closed cell geometry.

11. The transistor of claim 10 when said closed cell geometry is rectangular.

12. The transistor of claim 1 wherein at least one of said trench DMOS transistor cells has an open cell geometry.

13. The transistor of claim 1 further comprising a plurality of polysilicon contacts respectively connected to each of the conductive electrodes of the peripheral transistor cells.

14. A trench DMOS transistor structure that includes at least three individual trench DMOS transistor cells formed on a substrate of a first conductivity type, said plurality of individual DMOS transistor cells being dividable into peripheral transistor cells and interior transistor cells, each of said individual transistor cells comprising:

body region on the substrate, said body region having a second conductivity type, wherein said body region has a bimodal distribution across the width of the transistor cells in which they are respectively located;

at least one trench extending through the body region and the substrate;

an insulating layer that lines the trench;

a conductive electrode in the trench overlying the insulating layer; and

wherein at least said interior transistor cells each further include a source region of the first conductivity type in the body region adjacent to the trench, and wherein said at least one trench extends to a depth below the depth of said body region, and

further wherein the body regions of said peripheral transistor cells are more lightly doped than the body regions of said interior transistor cells.

15. The transistor structure of claim 14 further comprising a drain electrode disposed on a surface of the substrate opposing the body region.

16. The transistor stricture of claim 14 wherein said insulating layer is an oxide layer.

17. The transistor structure of claim 14 wherein said conductor electrode includes polysilicon.

18. The transistor of claim 14 wherein at least one of said trench DMOS transistor cells has a closed cell geometry.

19. The transistor of claim 18 when said closed cell geometry is rectangular.

20. The transistor of claim 14 wherein at least one of said trench DMOS transistor cells has an open cell geometry.

21. The transistor of claim 14 further comprising a plurality of polysilicon contacts respectively connected to each of the conductive electrodes of the peripheral transistor cells.

22. The transistor of claim 14 further comprising a plurality of polysilicon contacts respectively connected to each of the conductive electrodes of the