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Sub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gate

  • US 6,548,875 B2
  • Filed: 03/06/2001
  • Issued: 04/15/2003
  • Est. Priority Date: 03/06/2000
  • Status: Expired due to Fees
First Claim
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1. A transistor comprising:

  • a semiconductor substrate;

    a gate insulation film formed on the semiconductor substrate;

    a gate electrode formed on the gate insulation film;

    a channel region formed in the semiconductor substrate below the gate insulation film;

    a source region and a drain region formed to be spaced apart from each other in the semiconductor substrate, said channel region being between the source region and the drain region;

    a source semiconductor layer formed over the source region, said source semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the source semiconductor layer facing the gate electrode and a surface of the semiconductor substrate;

    a drain semiconductor layer formed over the drain region, said drain semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the drain semiconductor layer facing the gate electrode and the surface of the semiconductor substrate;

    a source electrode buried in the concave portion at the upper portion of the source semiconductor layer; and

    a drain electrode buried in the concave portion at the upper portion of the drain semiconductor layer, wherein said gate electrode, said drain electrode and said source electrode are formed of the same material selected from the group consisting of metal and metal silicide.

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