Sub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gate

• US 6,548,875 B2
• Filed: 03/06/2001
• Issued: 04/15/2003
• Est. Priority Date: 03/06/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nishiyama, Akira
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US09/798,924
• Publication Number:
  US 20020008261A1
• Time in Patent Office: 770 Days
• Field of Search: 257/288, 257/192, 257/330, 257/332, 257/410-411, 257/377, 257/382, 257/383
• US Class Current: 257/377
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 μm generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gate electrode without using selective metal growth methods. Further, after forming the gate electrode, a semiconductor film is temporarily formed selectively in source/drain regions. A dielectric film is next deposited on the substrate and then, the surface is etched by chemical/mechanical polish (CMP) techniques to the extent that the semiconductor film is exposed on the surface. The semiconductor film is then partly etched until its midway portion along the thickness is removed. Thereafter, a desired metal or silicide is deposited on the entire surface. Next, CMP etching is performed to form electrodes, while letting the electrodes reside on or over the source/drain semiconductor layers and a gate insulation layer.

Claims

1. A transistor comprising:

a semiconductor substrate;

a gate insulation film formed on the semiconductor substrate;

a gate electrode formed on the gate insulation film;

a channel region formed in the semiconductor substrate below the gate insulation film;

a source region and a drain region formed to be spaced apart from each other in the semiconductor substrate, said channel region being between the source region and the drain region;

a source semiconductor layer formed over the source region, said source semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the source semiconductor layer facing the gate electrode and a surface of the semiconductor substrate;

a drain semiconductor layer formed over the drain region, said drain semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the drain semiconductor layer facing the gate electrode and the surface of the semiconductor substrate;

a source electrode buried in the concave portion at the upper portion of the source semiconductor layer; and

a drain electrode buried in the concave portion at the upper portion of the drain semiconductor layer,

wherein said gate electrode, said drain electrode and said source electrode are formed of the same material selected from the group consisting of metal and metal silicide.

2. The transistor according to the claim 1, wherein the acute angle defined is 10°

or greater than 80°

or less.

3. The transistor according to the claim 1, wherein the acute angle defined is 20°

or greater and 70°

or less.

4. The transistor according to the claim 1, wherein the gate insulation film includes a materiel selected from the group consisting of metal oxide, metal nitride, metal oxynitride, and silicate.

5. The transistor according to the claim 1, wherein surfaces of the source semiconductor layer and the drain semiconductor layer in contact with the source electrode and the drain electrode respectively are formed by anisotropic etching.

6. The transistor according to the claim 1, wherein surfaces of the source semiconductor layer and the drain semiconductor layer in contact with the source electrode and the drain electrode respectively ale formed by isotropic etching.

7. A semiconductor device comprising:

a common semiconductor substrate;

an n-channel MISFET on the common semiconductor substrate and including;

a gate insulation film formed on the common semiconductor substrate,

a gate electrode formed on the gate insulation film,

a channel region formed in the common semiconductor substrate below the gate insulation film,

a source region and a drain region formed to be spaced apart from each other in the common semiconductor substrate, said channel region being between the source region and the drain region,

a source semiconductor layer formed over the source region, said source semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the source semiconductor layer facing the gate electrode and a surface of the common semiconductor substrate,

a drain semiconductor layer formed over the drain region, said drain semiconductor layer having a concave portion at an upped portion thereof and including an acute angle defined between a side face of the drain semiconductor layer facing the gate electrode and a surface of the common semiconductor substrate,

a source electrode buried in the concave portion at the upper portion of the source semiconductor layer, and

a drain electrode buried in the concave portion at the upper portion of the drain semiconductor layer; and

a p-channel MISFET on the common semiconductor substrate including;

a gate insulation film formed on the common semiconductor substrate,

a gate electrode formed on the gate insulation film,

a channel region formed in the common semiconductor substrate below the gate insulation film,

a source region and a drain region formed to be spaced apart from each other in the common semiconductor substrate, said channel region being between the source region and the drain region,

a source semiconductor layer formed over the source region, said source semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the source semiconductor layer facing the gate electrode and a surface of the common semiconductor substrate,

a drain semiconductor layer formed over the drain region, said drain semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the drain semiconductor layer facing the gate electrode and a surface of the common semiconductor substrate,

a source electrode buried in the concave portion at the upper portion of the source semiconductor layer, and

a drain electrode buried in the concave portion at the upper portion of the drain semiconductor layer,

wherein said gate electrode, said drain electrode and said source electrode of said n-channel MISFET are made of same material selected from metal and metal silicide, and

wherein said gate electrode, said drain electrode and said source electrode of said p-channel MISFET are made of same material selected from the group consisting of metal and metal silicide and said source electrode, said drain electrode and said gate electrode of said n-channel MISFET are different material from said source electrode, said drain electrode and said gate electrode of said p-channel MISFET.

8. The semiconductor device according to claim 7, wherein the gate electrode of the n-channel MISFET is different material from the gate electrode of the p-channel MISFET.