Apparatus and method for testing for compatibility between circuit boards

• US 6,549,027 B1
• Filed: 11/07/2000
• Issued: 04/15/2003
• Est. Priority Date: 02/01/2000
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Mott, James A.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US09/707,665
• Time in Patent Office: 889 Days
• Field of Search: 324/761, 324/759, 324/764, 324/763, 714/733, 714/734, 714/781, 710/8, 710/10, 710/62, 710/100, 713/100
• US Class Current: 361/679.02
• CPC Class Codes: H05K 7/1445 with double-sided connections

Abstract

An apparatus and method for comparing identifications of circuit boards in a midplane. When a first circuit board and a second circuit board are inserted into opposite sides of the midplane, an incompatibility between the first circuit board and the second circuit board may damage or impair the operation of one or both of the first circuit board and the second circuit board. To solve this problem, a first identification is stored on the first circuit board and a second identification is stored on the second circuit board. If the first identification of the first circuit board and the second identification of the second circuit board indicate an incompatibility, then one or both of the first circuit board and the second circuit board is/are prevented from fully powering up.

Claims

1. A method of checking compatibility between first and second circuit boards coupled to a midplane of a computer, comprising:

receiving at a second circuit board a first identifier of a first circuit board;

retrieving from a read-only memory in the second board a second identifier of the second circuit board; and

at the second circuit board, comparing the first identifier with the second identifier of the second circuit board to check compatibility between the first circuit board and the second circuit board.

2. The method of claim 1, wherein the second identifier identifies at least one of:

a type of the second circuit board; and

a version of the type of the second circuit board.

3. The method of claim 1, wherein said receiving comprises:

receiving the first identifier from a registry of identifiers of circuit boards.

4. The method of claim 1, further comprising:

responsive to the step of comparing, preventing one of the first circuit board and the second circuit board from fully powering up if an incompatibility is found.

5. The method of claim 1, further comprising:

serially communicating the first identifier to the second circuit board.

6. The method of claim 5, wherein the comparing includes comparing the first identifier to the second identifier one bit at a time.

7. A method of checking compatibility of first and second circuit boards in a midplane of a computer, comprising:

sending a first identifier from a first circuit board; and

comparing the first identifier to a predetermined second identifier of a second circuit board to check compatibility between the first circuit board and the second circuit board in the computer;

wherein said predetermined second identifier is stored prior to said sending.

8. The method of claim 7, wherein the first identifier identifies at least one of a type of the first circuit board and a version of the type of the first circuit board.

9. The method of claim 7, wherein the comparing step includes:

comparing the first identifier to a registry of identifications of circuit boards.

10. The method of claim 7, further comprising:

responsive to the step of comparing, preventing the first circuit board from fully powering up if an incompatibility is found.

11. The method of claim 7, wherein the first identifier is sent serially from the first circuit board.

12. The method of claim 11, wherein the comparing includes comparing the first identifier one bit at a time.

13. A method of checking compatibility between first and second circuit boards inserted into a midplane, comprising:

inserting into the midplane a first circuit board having a first memory holding a first identification;

inserting into the midplane a second circuit board having a second memory holding a second identification; and

comparing the first identification with the second identification to check compatibility between the first circuit board and the second circuit board.

14. The method of claim 13, further comprising:

if the first circuit board and the second circuit board are compatible, allowing at least one of the first circuit board and the second circuit board to fully power up; and

if the first circuit board and the second circuit board are incompatible, preventing one of the first circuit board and the second circuit board from fully powering up.

15. The method of claim 13, wherein checking compatibility includes checking a version of at least one of the first circuit board and the second circuit board.

16. The method of claim 13, wherein the first circuit board and the second circuit board are positioned on opposite sides of the midplane.

17. The method of claim 13, wherein the first circuit board and the second circuit board are positioned on a same side of the midplane.

18. The method of claim 13, further comprising:

communicating at least one of the first identification and the second identification serially from at least one of the first circuit board and the second circuit board.

19. The method of claim 18, wherein the comparing includes comparing the first identifier to the second identifier one bit at a time.

20. A circuit board, comprising:

a memory storing a predetermined identification of the circuit board,

a connector configured to receive a separate identification from a separate circuit board; and

circuitry coupled to the memory and the connector, wherein the circuitry compares the identification of the circuit board with the separate identification of the separate circuit board to check for compatibility between the circuit board and the separate circuit board.

21. The circuit board of claim 20, wherein at least one of the circuit board and the separate circuit board is prevented from fully powering up if the comparison of the identification with the separate identification indicates that the circuit board and the separate circuit board are incompatible.

22. The circuit board of claim 20, wherein at least one of the identification and the separate identification is communicated serially from at least one of the circuit board and the separate circuit board.

23. The circuit board of claim 22, wherein the circuitry compares the identification to the separate identification one bit at a time.

24. A computer system, comprising:

a midplane;

a first circuit board coupled to the midplane, including a first memory holding a first predetermined identification; and

a second circuit board coupled to the midplane, including a second memory holding a second predetermined identification;

wherein the first identification is compared with the second identification to check compatibility of the first circuit board with the second circuit board.

25. The computer system of claim 24, wherein at least one of the first circuit board and the second circuit board is prevented from fully powering up if the first identification and the second identification identify the first circuit board and the second circuit board as incompatible.

26. The computer system of claim 24, wherein at least one of the first identification and the second identification is communicated serially from at least one of the first circuit board and the second circuit board.

27. The computer system of claim 26, wherein the circuitry compares the first identification to the second identification one bit at a time.

29. The computer system of claim 24, further comprising:

a registry of circuit board identifiers, wherein said registry is coupled to the midplane.

28. A computer system, comprising:

a midplane;

a first circuit board configured for coupling to the midplane and comprising;

a read-only memory containing a first identifier of the first circuit board; and

a conductor for communicating the first identifier to the midplane;

a second circuit board configured for coupling to the midplane and comprising;

a read-only memory containing a second identifier of the second circuit board;

a conductor for receiving the first identifier;

logic for comparing the first identifier to the second identifier to determine whether the first circuit board and the second circuit board are compatible; and

an early power line configured to power said logic before the second circuit board is fully powered;

wherein the second circuit board is prevented from being fully powered if the first circuit board and the second circuit board are determined to be incompatible.

30. The computer system of claim 28, wherein the identifier of the first circuit board is carried serially through said conductors of the first circuit board and the second circuit board.