Hi gain clock circuit

• US 6,549,039 B1
• Filed: 09/27/2000
• Issued: 04/15/2003
• Est. Priority Date: 09/27/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rosen, Eitan E.
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US09/670,560
• Time in Patent Office: 930 Days
• Field of Search: 326/93, 326/95, 326/98, 326/83, 327/142, 327/198, 327/210
• US Class Current: 326/93
• CPC Class Codes: H03K 5/023 using field effect transistors
• CPC Class Codes: H03K 5/153 Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant switching at zero crossing H03K17/13
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A high gain clock circuit that includes an input section that receives an input clock on an input section input. A self terminating pre-charge section is connected to the input section and includes domino logic. An output section is connected to the self terminating pre-charge section and produces an output clock at an output section output. The clock circuit encompasses a small area and achieves high gain at the output section output relative to the input section input. The high gain clock circuit has higher gain than known circuits and is characterized by fast rise time and slower fall time.

Claims

1. A high gain clock circuit comprising:

input section, the input section receiving an input clock on an input section input;

a self terminating pre-charge section operatively connected to the input section, the self terminating pre-charge section including domino logic;

an output section operatively connected to the self terminating pre-charge section, the output section producing an output clock at an output section output,

wherein the output clock transitions from a low level to a high level approximately two device delays after the input clock transitions from a low level to a high level, and the output clock transitions from a high level to a low level approximately four device delays after the input clock transitions from a high level to a low level, the clock circuit encompassing a small area and achieving high gain at the output section output relative to the input section input.

2. The circuit according to claim 1, the input section further comprising:

an inverting device, the inverting device receiving the input clock on an inverting device input; and

a NAND device, a first input of the NAND device operatively connected to an output of the inverting device, a second input of the NAND device operatively connected to an output of the self terminating pre-charge section, an output of the NAND device operatively connected to an input of the self terminating pre-charge section.

3. The circuit according to claim 2, wherein the inverting device is an inverter logic gate.

4. The circuit according to claim 1, wherein the input clock is a waveform with a fifty percent duty cycle.

5. The circuit according to claim 2, wherein the first inverting device and the second inverting device comprise one of an inverter logic gate and a NAND logic gate.

6. A high gain clock circuit comprising:

a first inverting device, the first inverting device receiving a clock at an input of the first inverting device;

an n-type device, the n-type device connected to the input of the first inverting device, the n-type device receiving the clock input;

a second inverting device, an input of the second inverting device connected to an output of the n-type device, an output of the second inverting device producing an output clock;

a third inverting device, an input of the third inverting device connected to the output of the n-type device;

a fourth inverting device, an output of the fourth inverting device connected to the input of the second inverting device;

a NAND device, one NAND device input connected to an output of the third inverting device and an input of the fourth inverting device;

a p-type device connected to an output of the NAND device,

wherein the clock circuit encompasses a small area and achieves high gain at the output of the second inverting device relative to the input of the first inverting device,

wherein the output clock transitions from a low level to a high level approximately two device delays after the input clock transitions from a low level to a high level, and the output clock transitions from a high level to a low level approximately four device delays after the input clock transitions from a high level to a low level.

7. A high gain clock macro comprising:

an input section, the input section receiving an input clock on an input section input;

a self terminating pre-charge section operatively connected to the input section, the self terminating pre-charge section including domino logic;

an output section operatively connected to the self terminating pre-charge section, the output section producing an output clock at an output section output,

wherein the output clock transitions from a low level to a high level approximately two device delays after the input clock transitions from a low level to a high level, and the output clock transitions from a high level to a low level approximately four device delays after the input clock transitions from a high level to a low level, the clock macro encompassing a small area and achieving high gain at the output section output relative to the input section input.

8. An Integrated Circuit (IC) that receives an input signal and provides a high gain at an IC output comprising:

an input section, the input section receiving an input clock on an input section input;

a self terminating pre-charge section operatively connected to the input section, the self terminating pre-charge section including domino logic;

an output section operatively connected to the self terminating pre-charge section, the output section producing an output clock at an output section output,

wherein the output clock transitions from a low level to a high level approximately two device delays after the input clock transitions from a low level to a high level, and the output clock transitions from a high level to a low level approximately four device delays after the input clock transitions from a high level to a low level, the IC encompassing a small area and achieving high gain at the output section output relative to the input section input.

9. A high gain clock circuit comprising:

an input section, the input section receiving an input clock on an input section input, the input section including a first input with a logic signal A, the input section input with a logic signal B, a first output with a logic signal C, and a second output with a logic signal D, the input section comprising logic circuits where C=NOT A+(A*B), and D=B, the first output (C) and the second output (D) operatively connected to the self terminating pre-charge section;

a self terminating pre-charge section operatively connected to the input section, the self terminating pre-charge section including domino logic;

an output section operatively connected to the self terminating pre-charge section, the output section producing an output clock at an output section output, wherein the clock circuit encompassing a small area and achieving high gain at the output section output relative to the input section input.

10. A high gain clock circuit comprising:

an input section, the input section receiving an input clock on an input section input;

a self terminating pre-charge section operatively connected to the input section, the self terminating pre-charge section including domino logic, the self terminating pre-charge section further comprising;

a p-type device, an input of the p-type device operatively connected to a first output from the input section;

an n-type device, an input of the n-type device receiving the input clock from a second output from the input section;

a first inverting device, an input of the first inverting device operatively connected to an output from the n-type device and an output from the p-type device, an output from the n-type device operatively connected to the input section; and

a second inverting device, an input of the second inverting device operatively connected to the output of the first inverting device, an output of the second inverting device operatively connected to the input of the first inverting device and the output section; and

an output section operatively connected to the self terminating pre-charge section, the output section producing an output clock at an output section output,

wherein the clock circuit encompassing a small area and achieving high gain at the output section output relative to the input section input.

11. The circuit according to claim 10, wherein the first inverting device and the second inverting device comprise one of an inverter logic gate and a NAND logic gate.