Memory cell structure

• US 6,549,447 B1
• Filed: 10/31/2001
• Issued: 04/15/2003
• Est. Priority Date: 10/31/2001
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Fricke, Peter, Van Brocklin, Andrew L
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US10/001,740
• Publication Number:
  US 20030081446A1
• Time in Patent Office: 531 Days
• Field of Search: 365/105, 365/173, 365/225.7, 365/51, 365/63, 365/103, 365/114
• US Class Current: 365/105
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/8418 adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883

Abstract

A memory cell has a first and second conductor. The first conductor is oriented in a first direction and the second conductor is oriented in a second direction. The first conductor has at least one edge. A state-change layer is disposed on the first conductor and a control element is partially offset over the at least one edge of the first conductor. The control element is disposed between the first and second conductors. Preferably the state-change layer is a direct-tunneling or dielectric rupture anti-fuse. A memory array can be formed from a plurality of the memory cells. Optionally, creating multiple layers of the memory cells can form a three-dimensional memory array.

Claims

1. A memory cell, comprising:

a first conductor oriented in a first direction and having at least one edge;

a second conductor oriented in a second direction at a height different than the first conductor;

a state-change element disposed on the first conductor; and

a control element disposed between the first and second conductors wherein the control element is partially offset over the at least one edge of the first conductor.

2. The memory cell of claim 1 wherein the first conductor has a plurality of edges and wherein the control element is partially offset over the plurality of edges of the first conductor.

3. The memory cell of claim 1 wherein the plurality of edges of the first conductor intersect.

4. The memory cell of claim 1 wherein the first conductor is a metal from the group consisting of aluminum, copper, silicide and alloys thereof.

5. The memory cell of claim 1 wherein the state-change layer is fabricated by either oxidizing a portion of the first conductor or depositing a thin layer on the first conductor then oxidizing the thin layer.

6. The memory cell of claim 1 wherein the state-change layer is fabricated by depositing state-change material.

7. The memory cell of claim 1 wherein the state-change layer is fabricated by depositing phase-change material.

8. The memory cell of claim 1 wherein the control element is comprised of a morphous or microcrystalline silicon.

9. The memory cell of claim 1 wherein the control element has been fabricated with doping ramped from a first polarity dopant to a second polarity dopant.

10. The memory cell of claim 1 wherein the control element has been fabricated with doping ramped from a first polarity dopant, then substantially no dopant, to a second polarity dopant.

11. The memory cell of claim 1 wherein the control element is a tunnel junction device.

12. The memory cell of claim 1 wherein the state-change layer is a direct tunneling anti-fuse.

13. The memory cell of claim 1 wherein the state-change layer is a dielectric rupture anti-fuse.

14. The memory cell of claim 1 wherein the state-change layer is a LeComber or silicide switch.

15. The memory cell of claim 1 wherein the state-change layer is comprised of phase-change material.

16. A memory array comprised of a plurality of memory cells as in claim 1.

17. The memory array of claim 16 wherein the plurality of memory cells are formed in a three dimensional array.

18. A memory cell, comprising:

state-change means for programming a memory state with an electric field; and

means for increasing the electric field to lower the energy required to program the state-change means.

19. A memory cell, comprising:

a first conductor;

a second conductor disposed at a second height to the first conductor;

an state-change element disposed between the first conductor and the second conductor and substantially aligned with and disposed on the first conductor; and

a control element partially disposed between the first conductor and the state-change element and partially offsetting the state-change element.

20. A memory cell, comprising:

a first conductor having a first width;

a second conductor having a second width;

a control element having a first end surface with first opposite edges spaced-apart by a distance about equal to the first width and second opposite edges spaced apart by a distance equal to the second width where the first end surface is continuous contact with the second conductor, a second end surface; and

a state-change element connected in series with the control element, the state-change element disposed over the first conductor and partially contacted the second end surface of the control element wherein the control element and the state-change element are offset in vertical alignment.

21. A memory cell, comprising:

a first conductor having at least one edge;

a second conductor;

a control element disposed partially between the first and second conductor and offsetting over the at least one edge of the first conductor; and

a state-change element disposed between the first conductor and the control element and overlapping the at least one edge of the first conductor.

22. A memory cell, comprising:

a first conductor capable of creating an electric field;

a second conductor;

means for controlling current connected to the second conductor;

means for storing a state-change using the electric field of the first conductor, said means for storing disposed between the means for controlling current and the first conductor; and

means for enhancing the electric field of the first conductor.

23. The memory cell of claim 22 wherein the first conductor includes at least one edge and wherein the means for enhancing the electric field comprises offsetting the means for controlling current over the at least one edge the first conductor.

24. A method of making a memory cell on a substrate, comprising the steps of:

creating a first electrode having at least one edge on the substrate;

then creating a first state-change layer disposed over the first electrode including the at least one edge;

then creating a first control element that is disposed over the at least one edge of the first electrode and partially over first state change layer and offset partially beyond the at least one edge of the first electrode; and

then depositing a first dielectric layer over the processed substrate.

25. The method of claim 24 wherein the step of creating a first state-change layer comprises the step of oxidizing the first electrode.

26. The method of claim 24 wherein the step of creating a first state-change layer comprises the step of depositing a phase-change material.

27. The method of claim 24 further comprising the steps of:

planarizing the deposited dielectric layer; and

creating a second electrode having at least one edge, the second electrode orthogonal to the first electrode.

28. A method of programming a memory cell having a state-change element, comprising the step of increasing an electric field using a physical feature in a conductive trace contacting the state-change element.

29. A method of programming a memory cell having a state-change element, comprising the step of increasing the thermal energy presented to the state-change element by partially offsetting a control element connected to the state-change element thereby limiting thermal conduction.