Memory cell structure
First Claim
Patent Images
1. A memory cell, comprising:
- a first conductor oriented in a first direction and having at least one edge;
a second conductor oriented in a second direction at a height different than the first conductor;
a state-change element disposed on the first conductor; and
a control element disposed between the first and second conductors wherein the control element is partially offset over the at least one edge of the first conductor.
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Abstract
A memory cell has a first and second conductor. The first conductor is oriented in a first direction and the second conductor is oriented in a second direction. The first conductor has at least one edge. A state-change layer is disposed on the first conductor and a control element is partially offset over the at least one edge of the first conductor. The control element is disposed between the first and second conductors. Preferably the state-change layer is a direct-tunneling or dielectric rupture anti-fuse. A memory array can be formed from a plurality of the memory cells. Optionally, creating multiple layers of the memory cells can form a three-dimensional memory array.
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Citations
29 Claims
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1. A memory cell, comprising:
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a first conductor oriented in a first direction and having at least one edge;
a second conductor oriented in a second direction at a height different than the first conductor;
a state-change element disposed on the first conductor; and
a control element disposed between the first and second conductors wherein the control element is partially offset over the at least one edge of the first conductor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory cell, comprising:
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state-change means for programming a memory state with an electric field; and
means for increasing the electric field to lower the energy required to program the state-change means.
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19. A memory cell, comprising:
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a first conductor;
a second conductor disposed at a second height to the first conductor;
an state-change element disposed between the first conductor and the second conductor and substantially aligned with and disposed on the first conductor; and
a control element partially disposed between the first conductor and the state-change element and partially offsetting the state-change element.
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20. A memory cell, comprising:
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a first conductor having a first width;
a second conductor having a second width;
a control element having a first end surface with first opposite edges spaced-apart by a distance about equal to the first width and second opposite edges spaced apart by a distance equal to the second width where the first end surface is continuous contact with the second conductor, a second end surface; and
a state-change element connected in series with the control element, the state-change element disposed over the first conductor and partially contacted the second end surface of the control element wherein the control element and the state-change element are offset in vertical alignment.
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21. A memory cell, comprising:
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a first conductor having at least one edge;
a second conductor;
a control element disposed partially between the first and second conductor and offsetting over the at least one edge of the first conductor; and
a state-change element disposed between the first conductor and the control element and overlapping the at least one edge of the first conductor.
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22. A memory cell, comprising:
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a first conductor capable of creating an electric field;
a second conductor;
means for controlling current connected to the second conductor;
means for storing a state-change using the electric field of the first conductor, said means for storing disposed between the means for controlling current and the first conductor; and
means for enhancing the electric field of the first conductor. - View Dependent Claims (23)
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24. A method of making a memory cell on a substrate, comprising the steps of:
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creating a first electrode having at least one edge on the substrate;
then creating a first state-change layer disposed over the first electrode including the at least one edge;
then creating a first control element that is disposed over the at least one edge of the first electrode and partially over first state change layer and offset partially beyond the at least one edge of the first electrode; and
then depositing a first dielectric layer over the processed substrate. - View Dependent Claims (25, 26, 27)
planarizing the deposited dielectric layer; and
creating a second electrode having at least one edge, the second electrode orthogonal to the first electrode.
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28. A method of programming a memory cell having a state-change element, comprising the step of increasing an electric field using a physical feature in a conductive trace contacting the state-change element.
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29. A method of programming a memory cell having a state-change element, comprising the step of increasing the thermal energy presented to the state-change element by partially offsetting a control element connected to the state-change element thereby limiting thermal conduction.
Specification