Nonvolatile semiconductor memory device

• US 6,549,464 B2
• Filed: 07/02/2002
• Issued: 04/15/2003
• Est. Priority Date: 05/14/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shirota, Riichiro, Fujimura, Susumu, Arai, Fumitaka, Takeuchi, Ken, Tanaka, Tomoharu, Nakamura, Hiroshi
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US10/187,285
• Publication Number:
  US 20030035316A1
• Time in Patent Office: 287 Days
• Field of Search: 365/185.17, 365/185.03, 365/185.22, 365/185.24, 365/185.3
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3463 Circuits or methods to detect overprogrammed nonvolatile memory cells, usually during program verification
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Claims

1. A nonvolatile semiconductor memory device comprising:

a plurality of nonvolatile semiconductor memory cells, each capable of storing n-value data, where n is a natural number greater than 2; and

a data-programming circuit for performing a program operation in which program pulses are applied to said plurality of nonvolatile semiconductor memory cells to program n-value data into said plurality of nonvolatile semiconductor memory cells, performing a program verification operation to determine whether or not the n-value data has been programmed into said plurality of nonvolatile semiconductor memory cells and repeating the program operation and the program verification operation, wherein each of said program pulses has a predetermined pulse width in accordance with a value of the n-value data to be programmed into a corresponding memory cell.

2. The memory device according to claim 1, in which each program pulse is removed from said corresponding memory cell after the program verification operation determines that n-value data has been programmed into said corresponding memory cell.

3. The memory device according to claim 1, in which the program operation is terminated when the program verification operation determines that all of n-value data have been programmed into said plurality of nonvolatile semiconductor memory cells.

4. The memory device according to claim 1, in which the program operation and the program verification operation are terminated after a limited number of cycles.

5. The memory device according to claim 1, in which said plurality of nonvolatile semiconductor memory cells are connected to one word line.

6. The memory device according to claim 1, in which said plurality of memory cells are respectively included in corresponding NAND cell units, each NAND cell unit comprising a predetermined number of nonvolatile semiconductor memory cells connected in series, and in the program operation, said data-programming circuit applying a first voltage to at least one of the two memory cells adjacent to said selected memory cells to be programmed and a second voltage to the remaining memory cells.

7. The memory device according to claim 6, in which voltages of the program pulses are greater than the first and second voltages, and the second voltage is greater than the first voltage.

8. The memory device according to claim 7, in which the first voltage is 0V.