Nonvolatile semiconductor memory device
First Claim
1. A nonvolatile semiconductor memory device comprising:
- a plurality of nonvolatile semiconductor memory cells, each capable of storing n-value data, where n is a natural number greater than 2; and
a data-programming circuit for performing a program operation in which program pulses are applied to said plurality of nonvolatile semiconductor memory cells to program n-value data into said plurality of nonvolatile semiconductor memory cells, performing a program verification operation to determine whether or not the n-value data has been programmed into said plurality of nonvolatile semiconductor memory cells and repeating the program operation and the program verification operation, wherein each of said program pulses has a predetermined pulse width in accordance with a value of the n-value data to be programmed into a corresponding memory cell.
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Accused Products
Abstract
A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
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Citations
8 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a plurality of nonvolatile semiconductor memory cells, each capable of storing n-value data, where n is a natural number greater than 2; and
a data-programming circuit for performing a program operation in which program pulses are applied to said plurality of nonvolatile semiconductor memory cells to program n-value data into said plurality of nonvolatile semiconductor memory cells, performing a program verification operation to determine whether or not the n-value data has been programmed into said plurality of nonvolatile semiconductor memory cells and repeating the program operation and the program verification operation, wherein each of said program pulses has a predetermined pulse width in accordance with a value of the n-value data to be programmed into a corresponding memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification