High-speed serial data communication system

• US 6,549,595 B1
• Filed: 12/29/1998
• Issued: 04/15/2003
• Est. Priority Date: 07/24/1998
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Pelgrom, Marcellinus J. M., Den Besten, Gerrit W.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Lugo, David B.
• Application Number:
  US09/222,397
• Time in Patent Office: 1,568 Days
• Field of Search: 375/360, 375/359, 375/354, 375/355, 375/242, 341/71
• US Class Current: 375/360
• CPC Class Codes: H04L 1/246 two-level transmission codes, e.g. binary
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0066 detection of error based on transmission code rule

Abstract

A serial communication system transfers respective first and second signals via respective parallel signal carriers from a transmitter circuit to a receiver circuit. In synchronization with a clock signal (150), the transmitter circuit (110) serially represents a combination of the clock signal and data bit(s) (160) of a data message as the first and second signals (130, 140). At a data bit boundary, the transmitter circuit effects a transition of the first signal (130) if the data bit to be transmitted has a first value and effects a transition of the second signal (140) if the data bit has a different second value. The receiver circuit (120) recovers the clock signal by detecting and combining signal transitions of the first and second signal, for instance using an XOR function, and recovers the data message from the first and/or the second signal.

Claims

1. A serial communication system comprising:

at least one transmitter circuit and at least one receiver circuit interconnected via a communication medium;

the communication medium providing at least a first and a second parallel signal carrier for transporting a respective first and second signal from the transmitter circuit to the receiver circuit;

the transmitter circuit comprising means for, in synchronization with a clock signal, serially representing a combination of the clock signal and data item(s) of a data message as the first and second signal such that at a data item boundary a signal transition occurs in either the first or the second signal; and

the transmitter circuit is operative to cause a transition of the first signal at a data item boundary preceding data item d of the data message if a function f(d) of the data item d has a first value and to cause a transition of the second signal at the data item boundary if the function f(d) has a different second value, and

the receiver circuit comprising means for recovering the clock signal by detecting and combining signal transitions of the first and second signal and for receiving the data message from the first and/or the second signal;

characterized in that the data item is a data bit and that the receiver circuit comprises first data bit recovery means which is operative to;

sample the first signal in synchronization with the recovered clock signal;

compare a sampled value b_i+1 sampled at instant t_i+1 to a sampled value b_i sampled at an instant t_i immediately preceding instant t_i+1; and

determine that the function f(d_i+1) of data bit d_i+1 has the first value if b_i≠

b_i+1 and that f(d_i+1) has the second value if b_i=b_i+1.

2. The serial communication system as claimed in claim 1, characterized in that the data item is a data bit and that the receiver circuit comprises second data bit recovery means, being operative to:

sample the second signal in synchronization with the recovered clock signal;

compare a sampled value b_i+1 sampled at instant t_i+1 to a sampled value _bi sampled at an instant t_i immediately preceding instant t_i+1;

determine that the function f(d_i+1) of data bit d_i+1 has the first value if b_i=b_i+1 and that f(d_i+1) has the second value if b_i≠

b_i+1.

3. The serial communication system as claimed in claim 2, characterized in that the receiver circuit comprises error detection means being operative to detect that an error has occurred if f(d_i+1) as determined by the first data bit recovery means differs from f(d_i+1) as determined by the second data bit recovery means.

4. The serial communication system as claimed in claim 1, characterized in that the receiver circuit comprises means for converting a plurality of serial samples to a parallel sample word and performs the comparison of the sampled value b_i+1 to the sampled value b_i on the parallel samples.

5. The serial communication system as claimed in claim 1, characterized in that f(d)=d.

6. The serial communication system as claimed in claim 1, characterized in that the function f(d) is a binary combination of the data bit d with at least one bit of a predetermined codeword.

7. The serial communication system as claimed in claim 1, characterized in that the transmitter circuit comprises means for transmitting a stream of variable length data messages by, after having completed transmission of a message of the stream, maintaining the first and second signal substantially at a respective constant level for a delay period of at least one data bit period as indicated by the clock signal, and enabling transmission of a following message of the stream after the delay period has expired;

and in that the receiver circuit comprises means for determining whether, for substantially more than one data item period, no signal transition occurs in both the first and second signal and, if so, determining that a message has ended.

14. The serial communication system as claimed in claim 6 wherein the binary combination comprises an XOR operation.

15. The serial communication system as claimed in claim 1 wherein the means for recovering the clock signal detects edges in the first and second signals.

8. A receiver apparatus comprising a receiver circuit comprising:

means for receiving a first and second signal from a transmitter circuit via parallel signal carriers;

means for recovering a clock signal by detecting and combining signal transitions of the first and second signal; and

means for recovering a data message from the first and/or the second signal;

characterized in that the receiver circuit is operative to determine whether substantially at a data bit boundary, as derived from the recovered clock signal, a transition occurred in the first or the second signal and to determine that a data item with a first value has been received if a transition occurred in the first signal and that a data item with a different second value has been received if a transition occurred in the second signal.

16. A receiver apparatus as claimed in claim 8 wherein the data item is a data bit and the receiver circuit comprises data bit recovery means operative to;

sample one of the first and second signals in synchronism with the recovered clock signal,

compare a first sampled value sample at a first instant to a second sample value sampled at a second instant immediately preceding the first instant, and

determine whether the data bit has a first or second value based on such comparison.

17. A receiver apparatus as claimed in claim 16 wherein the receiver circuit comprises means for converting a plurality of serial samples to a parallel sample word and performs the comparison on the first and second sampled parallel values.

18. The receiver circuit as claimed in claim 8, characterized in that the receiver circuit comprises means for detecting whether a signal transition occurred in the first and/or the second signal and determining a value of f(d) in dependence on the detection outcome, wherein f(d) is a function of a data item d of the data message.

9. A method of serially communicating between at least one transmitter circuit and at least one receiver circuit interconnected via a communication medium;

the communication medium providing at least a first and a second parallel signal carrier for transporting a respective first and second signal from the transmitter circuit to the receiver circuit;

wherein the method comprises;

in synchronization with a clock signal, serially encoding a combination of the clock signal and data items(s) of a data message as the first and second signal such that at a data item boundary a signal transition occurs in either the first or the second signal;

wherein the encoding comprises causing a transition of the first signal at a data item boundary preceding data item d of the data message if a function f(d) of the data item d has a first value and causing a transition of the second signal at the data item boundary if the function f(d) has a different second value;

outputting the first and second signal from the transmitter circuit via the respective first and second signal carriers;

inputting the first and second signals from the respective first and second signal carriers into the receiver circuit;

decoding the first and second signals for recovering the clock signal by detecting and combining signal transitions of the first and second signal; and

recovering the data message from the first and/or the second signal;

characterized in that;

the data item is a data bit and that the decoding comprises;

sampling the first signal in synchronization with the recovered clock signal;

comparing a sampled value b_i+1 sampled at instant t_i+1 to a sampled value b_i sampled at an instant t_i immediately preceding instant t_i+1; and

determining that the function f(d_i+1) of data bit d_i+1 has the first value if b_i≠

b_i+1 and that f(d_i+1) has the second value if b_i=b_i+1.

10. The communication method as claimed in claim 9 wherein the data message is recovered from the first and/or second signal.

11. The communication method as claimed in claim 10 wherein f(d)=d.

12. The communication method as claimed in claim 9 wherein the function f(d) is a binary combination of the data bit d with at least one bit of a predetermined codeword.

13. A method of serially communicating between at least one transmitter circuit and at least one receiver circuit interconnected via a communication medium;

the communication medium providing at least a first and a second parallel signal carrier for transporting a respective first and second signal from the transmitter circuit to the receiver circuit;

wherein the method comprises;

in synchronization with a clock signal, serially encoding a combination of the clock signal and data items(s) of a data message as the first and second signal such that at a data item boundary a signal transition occurs in either the first or the second signal;

wherein the encoding step comprises transferring data bits to the encoded signals by means of an XOR function, outputting the first and second signal from the transmitter circuit via the respective first and second signal carriers;

inputting the first and second signals from the respective first and second signal carriers into the receiver circuit;

decoding the first and second signals for recovering the clock signal by detecting and combining signal transitions of the first and second signal; and

recovering the data message from the first and/or the second signal as derived from the recovered clock signal;

and the decoding step comprises transforming the encoded signals into the data bits by means of an XOR function, and wherein

the encoding comprises causing a transition of the first signal at a data item boundary preceding data item d of the data message if a function f(d) of the data item d has a first value and causing a transition of the second signal at the data item boundary if the function f(d) has a different second value.